Unversität Zürich

Other

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Giacomo Indiveri

Thomas Dalgaty

Manu Vijayagopalan Nair

Fabio Stefanini

Saber Moradi

Melika Payvand

Ning Qiao

Elisas Vianello

The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell () having an input coupled to a first input line () of the routing circuit and an output coupled to a first column line (); a second memory cell () having an input coupled to a second input line () of the routing circuit and an output coupled to the first column line (); and a first comparator circuit () configured to compare a signal (IREAD) on the first column line () with a reference level, and to selectively assert a signal (VOUT) on a first output line () of the routing circuit based on the comparison.

Neuromorphic architecture

Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits () particularly arranged on several units (), wherein each core circuit () comprises: an electronic array () comprising a plurality of computing nodes () and a plurality of memory circuits () which is configured to receive incoming events, wherein each computing node () is configured to generate an event comprising a data packet when incoming events received by the respective computing node () satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R) for providing intra-core connectivity and/or delivering events to intermediate level second router (R) for inter-core connectivity and to higher level third router (R) for inter-unit connectivity, and a broadcast driver () for broadcasting incoming events to all the memory circuits () in the core circuit () in parallel.

Networks and hierarchical routing fabrics with heterogeneous memory structures for scalable event-driven computing systems

A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.

Differential memristive circuit

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Zurich, Switzerland

Giacomo Indiveri