Stmicroelectronics S.r.l.

Marvell International Limited

Synopsys, Inc.

Giacomino Bollati

Melchiorre Bruccoleri

Marco Pio Demicheli

Daniele Ottini

Salvatore Portaluri

Stefano Marchese

Maurizio Malfa

Marco Bongiorni

Marco Gaeta

Ezio Galbiati

Rinaldo Castello

Roberto Alini

Maurizio Nessi

Giovanni Cesura

Luca Schillaci

Guido Gabriele Albasini

Alessandro Bosi

Pierandrea Savo

Luca Celant

Davide Demicheli

Edoardo Contini

Choon Haw Leong

Marco De Micheli

Alex Lollio

Alberto Minuti

A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.

Phase mismatch detection for a multiphase system

In one embodiment, the present disclosure includes an amplifier comprising first and second output stages. The first output stage receives first power supply voltages and the second output stage receives second power supply voltages greater than the first power supply voltages. A switching stage configures the output stages to provide a first current to an amplifier output node from the first output stage when a magnitude of a voltage on the output node is below a first value, provide a second current to the output node from the second output stage when the magnitude of the voltage on the output node is above a second value greater than the first value, and provide a third current to the output node from both the first output stage and the second output stage when the magnitude of the voltage on the output node is between the first value and the second value.

Circuits and methods for amplifying signals

A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.

Read/write transducer for a ferroelectric storage medium, and corresponding storage device and method

A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Circuit for correcting signal distortions

A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.

Logarithmic linear variable gain CMOS amplifier

An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop.

Low noise AC differential amplifier with reduced low corner frequency and current consumption

An AC differential amplifier includes a pair of identical differential transconductance stages. Each transconductance stage includes a pair of inputs and a pair of outputs. The pairs of output of the transconductance stages are connected in common, and form a pair of output nodes of the AC differential amplifier. The pair of output nodes is also connected to a supply line through respective load resistors. One input of one transconductance stage is coupled through a capacitive device to an input of the other transconductance stage. The other inputs of the transconductance stages form the input terminals of the AC differential amplifier.

AC differential amplifier with reduced low corner frequency

A step gain-variable CMOS amplifier includes an input pair of transistors, a bias current generator connected between a common source node of the input pair of transistors and a ground node, and a pair of load transistors. The pair of load transistors is connected between a supply voltage node and, respectively, to the drain nodes of the input pair of transistors. The CMOS amplifier includes a plurality of second input pairs of transistors to be connected in parallel to the input pair of transistors for increasing the effective width of the resultant transistors. Alternativelty, the CMOS amplifier includes a plurality of second load pairs of transistors to be connected in parallel to the load pair of transistors for increasing the effective width of the resultant transistors. Pairs of path selection switches may be programmably closed for connecting in parallel the selected pairs of transistors.

Step gain-variable CMOS amplifier

A full-wave rectifier for monitoring the amplitude of a differential analog signal includes a differential Track&Hold stage controlled by a first differential logic timing signal tracking the differential analog input signal during a tracking phase that corresponds to a high logic stage of the first differential timing signal. This produces a differential output signal that is a replica of the input signal and the signal is stored during a successive storing phase that corresponds to a low logic state of the first differential timing signal. A first differential output amplifier includes inputs coupled to the output of the Track&Hold stage. A differential bistable circuit, controlled by a second differential logic timing signal, includes inputs coupled to the differential outputs of the first amplifier and produces a third differential logic control signal. A second multiplexed amplifier, controlled by the third differential control signal, includes inputs coupled to the output of the Track&Hold stage and produces a differential analog signal having an amplitude function corresponding to the amplitude of the differential input signal. A timing circuit receives at an input a differential logic synchronizing signal and generates the first differential timing signal of the Track&Hold stage and the second differential timing signal of the bistable circuit.

High frequency track and hold full-wave rectifier

A method of equalizing a read channel of a mass magnetic memory device comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order in a range from 6 to 8 and a boost is implemented by introducing two real and opposed zeroes in the transfer function of the filter without altering the group delay.

Read channel equalization with enhanced signal to noise ratio

A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Optimization of the parameters of a pre-equalization low pass filter for a read channel

A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

Analog equalization low pass filter structure

A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Analog-to-digital flash converter for generating a thermometric digital code

A transconductor includes a differential stage formed by a pair of input transistors, and a resistive line of degeneration connecting the sources of the input transistors. A bias current generator is coupled between the source of each input transistor and ground. The resistive line of degeneration is formed by one or more transistors connected in series, the gates of which are coupled to a voltage reference. The voltage reference is at least equal to the common mode voltage of the differential stage. The one or more transistors forming the resistive line of degeneration are sized to operate in the triode region.

MOS transconductor with broad trimming range

A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.

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Castel San Giovanni, Italy

Giacomino Bollati