Samsung Electronics Co., Ltd.

Gi-young Yang

Tae-Joong Song

Sang-Hoon Baek

Ha-Young Kim

Jong-Hoon Jung

Jin-Young Lim

In-gyum Kim

Jae-Woo Seo

Dal-Hee Lee

Sung-Wee Cho

Jae-Ho Park

Sang-Kyu Oh

Jin-tae Kim

Hyo-Sig Won

Sang-hun Lee

Jin-Hyun Noh

Sung-Hyun Park

Kang-Hyun Baek

Woo-Jin Rim

Chi-Hwan Lee

Si-ho Jang

Jeong-Ho Do

A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

Integrated circuit including standard cell

A cooking device is provided, which includes a cooking portion, a hood portion arranged on the cooking portion and provided with a suction port formed on one side thereof, and a driving portion configured to move the hood portion, wherein the hood portion is movable to any one of a first position in which the hood portion is accommodated in the cooking portion and a second position in which the hood portion projects from the cooking portion, and an angle of the hood portion is varied so as to change a direction in which the suction port is directed in the second position.

Cooking device

An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

Methods of generating integrated circuit layout using standard cell library

A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Standard cell library and methods of using the same

A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

Method and system for designing semiconductor device

A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device

In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Sense amplifiers and memory devices having the same

A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.

Method of detecting degradation of semiconductor devices and method of detecting degradation of integrated circuits

An improved method for extrapolating worst-case Simulation Program with Integrated Circuit Emphasis (SPICE) model parameters for an integrated circuit including manufacturing semiconductor devices, measuring typical data and worst-case data with respect to various electrical characteristics of the manufactured devices, determining a set of typical SPICE model parameters using the typical data, and determining a set of worst-case SPICE model parameters using the typical data and the worst-case data. Determining the set of worst-case SPICE model parameters preferably includes extrapolating statistical model parameters using the typical data and the worst-case data and determining the set of worst-case SPICE model parameters using the statistical model parameters.

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Seoul, South Korea

Gi-young Yang