Skhynix Inc.

Seoul National University

Gi Moon Hong

Dae Han Kwon

Kyung Hoon Kim

Kyu Dong Hwang

Dong Hyun Kim

Suhwan Kim

Ji Hyo Kang

Dong Yoon Ka

Kyu Young Kim

Jae Hyeok Yang

Shin Hyun Jeong

A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

Test circuit and receiving circuit having test function

An integrated circuit includes an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation. The integrated circuit also includes a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.

Signal line sense amplifying circuit and integrated circuit capable of calibrating driving strength of MOS transistors

A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Pipe register control signal generation circuit and semiconductor apparatus including the same

A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Semiconductor device for calculating and calibrating delay amount

A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Semiconductor device related to operation of internal circuits

A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

Clock signal processing circuit, semiconductor apparatus, and semiconductor system

A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Phase correction circuit, clock buffer and semiconductor apparatus including the same

A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.

Semiconductor apparatus and data processing system including the semiconductor apparatus

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Bias generation circuit, buffer circuit including the bias generation circuit and semiconductor system including the buffer circuit

A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Clock compensation circuit

A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Semiconductor device for controlling voltage at an input node of a circuit during a low power mode

A semiconductor apparatus may include a command receiving circuit, a multiplexing circuit, and a DQ circuit. The command receiving circuit may be configured to latch signal bits of a command according to a clock signal, and output the latched signal bits as latched signals. The multiplexing circuit may be configured to receive the latched signals from the command receiving circuit, and selectively output the latched signals according to a flag signal which is internally generated within the semiconductor apparatus. The DQ circuit may be configured to receive the selectively outputted latched signals from the multiplexing circuit and receive the flag signal, and configured to output the selectively outputted latched signals and the flag signal as a feedback command to the outside of the semiconductor apparatus through a plurality of DQ pins.

Semiconductor apparatus, command training system, and command training method

A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.

Semiconductor apparatus and semiconductor system with training function

A semiconductor system includes a slave and a master, wherein the slave includes a plurality of unit memory regions, and is configured to transmit determination result data generated by comparing reference data and test data, to the master, and wherein the master is configured to write the reference data and the test data in the plurality of unit memory regions.

Growing community of inventors

Icheon-si, South Korea

Gi Moon Hong