Samsung Electronics Co., Ltd.

Gi-Jung Kim

Young-Nam Kim

Young-Sam Lim

Tae-Yeol Heo

Pil-Kyu Kang

Young-Soo Park

Sang-Mun Chon

Kyoo-chul Cho

Sam-jong Choi

Kyoo-Chul Cho

Hoe-Sik Chung

Shin-Hyeok Han

Yeon-Sook Kim

Woo-Serk Kim

Sook-Hyun Park

An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.

Gettering structures and methods and their application

The surface(s) of a polishing pad for polishing an object has a first portion including hydrophilic material and a second portion including hydrophobic material. The first portion of the polishing surface is located in a first region of the polishing pad and the second portion of the polishing surface is located in a second region of the polishing pad juxtaposed with the first region in the radial direction of the pad. The hydrophilic material may be a polymer resin that contains hydrophilic functional groups having OH and/or &#x2550;O at bonding sites of the polymer. The hydrophobic material may be a polymer resin that contains hydrophobic functional groups having H and/or F at bonding sites of the polymer. The polishing pad is manufactured by extruding respective lines of the hydrophilic and hydrophobic materials. The extruders and a backing are moved relative to each other such that the lines form concentric rings of the hydrophilic and hydrophobic materials.

Polishing pad of a chemical mechanical polishing apparatus and method of manufacturing the same

A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

Semiconductor wafer having identification indication

Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.

Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination

An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

Apparatus for analyzing a substrate employing a copper decoration

Growing community of inventors

Gyeonggi-do, South Korea

Gi-Jung Kim