International Business Machines Corporation

Globalfoundries Inc.

Gi-Joon Nam

Charles Jay Alpert

Paul Gerard Villarrubia

Shyam Ramji

Lakshmi Narasimha Reddy

Gustavo Enrique Tellez

Zhuo Li

Natarajan Viswanathan

Benjamin Neil Trombley

Chin Ngai Sze

Myung-Chul Kim

Hua Xiang

Taraneh Taghavi

Alexey Y Lvov

Ying Zhou

Stephen Thomas Quay

Jiang Hu

Jarrod Alexander Roy

Woohyun Chung

Dharmendra S Modha

Myron Dale Flickner

Pallab Datta

David Anthony Papa

Jinwook Jung

Jente Benedict Kuang

Sourav Saha

Haoxing Ren

Sven Peyer

Roman Vaculin

Alexander Joel Suess

James Thomas Rayfield

Ronald Dennis Rose

Shawn P Authement

Arjen Alexander Mets

Venkata Sitaramagiridharganesh Ganapavarapu

Rongjian Liang

Jennifer Kazda

David James Hathaway

Kanak Behari Agarwal

Yao-Wen Chang

Richard Harold Boivie

Diwesh Pandey

Yaoguang Wei

Christopher J Berry

Michael H Wood

Mehmet Can Yildiz

Robert Alan Philhower

Thomas Edward Rosser

Enriquillo Valdez

Janani Mukundan

Brian C Wilson

Michael Kazda

Manikandan Viswanath

Andrew D Huber

Frank Musante

Cindy ShuiKing Washburn

Michael W Dotson

David John Geiger

William R Migatz

Zhou Li

Chau-Chin Huang

Dongki Kim

John L McCann

Natarajan Vishvanathan

Sherief Mohamed Reda

Gary Robert Ellis

Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program ('ILP') operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit

A method, computer system, and a computer program product for managing digital assets is provided. The present invention may include receiving, in a second blockchain network, an authentication request to determine an authenticity of a new digital asset. The present invention may include determining, in the second blockchain network, the authenticity of the new digital asset. The present invention may include updating, in the second blockchain network, the authenticity of the new digital asset as authentic in a shared library. The present invention may include generating, in the second blockchain network, an update authenticity transaction, wherein the update authenticity transaction is sent to a first blockchain network.

Tracing and verifying a shared library using blockchain

Design rule violations ('DRVs') may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Rule check heatmap prediction

Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Short net pin alignment for routing

Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

Enhanced alignment for global placement in a circuit

Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

Power staple avoidance for routing via reduction

Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

Multi-stage electronic design automation parameter tuning

A method verifies an authenticity, integrity, and provenance of outputs from steps in a process flow. One or more processor(s) validate one or more inputs to each step in a process flow by verifying at least one of a hash and a digital signature of each of the one or more inputs. The processor(s) then generate digital signatures that cover outputs of each step and the one or more inputs to each step, such that the digital signatures result in a chain of digital signatures that are used to verify an authenticity, an integrity and a provenance of outputs of the one or more steps in the process flow.

Electronically verifying a process flow

Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Time-driven placement and/or cloning of components for an integrated circuit

Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

Fault-tolerant power-driven synthesis

A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

White space insertion for enhanced routability

Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

Dynamic SADP region generation

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Memory element graph-based placement in integrated circuit design

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

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Austin, TX, United States of America

Gi-Joon Nam