Samsung Electronics Co., Ltd.

Gi-jong Park

Bo-un Yoon

Sang-rok Hah

Young-rae Park

Jung-Yup Kim

Hong-kyu Hwang

Jun-shik Bae

Gee-won Nam

An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

Methods of planarizing insulating layers on regions having different etching rates

Growing community of inventors

Kyungki-do, South Korea

Gi-jong Park