Skhynix Inc.

Gi Jo Jeong

Do Hun Kim

Kwang Sun Lee

Seung Duk Cho

In Yong Jung

Ji Woon Yang

Woo Tae Chang

The present disclosure relates to a memory system capable of encrypting and storing data, and a memory controller. The memory controller may include a first interface configured to perform data communication with a first external device, a second interface configured to generate a signal for controlling an operation of a second external device and transmit the signal; and a processor configured to receive, from the first external device, a data write command to write data to the second external device, encrypt the data by using one of a plurality of keys stored in a key area provided in the first external device in response to the data write command, and then control the encrypted data to be written to the second external device.

Memory system, memory controller and operation method thereof for encrypting data stored in a nonvolatile memory

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device

A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Memory system and operating method of memory system storing doorbell information in the buffer memory

A memory controller may include a host interface controller, a first queue, a second queue, and a cache memory. The host interface controller may be configured to generate, based on a request received from a host, one or more command segments corresponding to the request. The first queue may be configured to store the one or more command segments. The second queue may be configured to store a target command segment from among the one or more command segments. The memory controller caches a target map segment corresponding to the target command segment into the cache memory in response to the target command segment being transferred from the first queue to the second queue.

Growing community of inventors

Icheon, South Korea

Gi Jo Jeong