Sun Microsystems, Inc.

Ghun Kim

Yet-Ping Pai

One embodiment of the present invention provides a system that facilitates placing flip-flops in an integrated circuit based on timing requirements. The system operates by first receiving a netlist for flip-flop connectivity. Next, the system determines a metal layer class definition for each signal in the netlist based upon timing requirements of a corresponding flip-flop. The system then classifies a flip-flop instance using the metal layer class definition by defining a flip-flop type for each flip-flop instance and associating the flip-flop with a group of other flip-flops that have a same metal layer class definition. Finally, determining a position for the group by replacing an existing repeater in the integrated circuit with the group of flip-flops.

Method and apparatus for grouping flip-flops by timing

One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to determine a noise and propagation delay effect through the given net.

Growing community of inventors

Sunnyvale, CA, United States of America

Ghun Kim