Qualcomm Incorporated

Gheorghe Calin Cascaval

Dario Suarez Gracia

Han Zhao

Behnam Robatmili

Arun Raman

Pablo Montesinos Ortego

Aravind Natarajan

Dexter Tamio Chun

Bohuslav Rychlik

Bin Wang

Luis Henrique Ceze

Subrato Kumar De

Richard Alan Stewart

Mohammad H Reshadi

Tushar Kumar

Madhukar Nagaraja Kedlaya

Mark S Fowler

Andrey Ermolinskiy

Rajarshi Gupta

Vinay Sridhara

Moinul H Khan

James Xenidis

Mihai Christodorescu

Martin Renschler

Ronald Alton

Idreas Mir

Mastooreh Salajegheh

Mehrad Tavakoli

Babak Salamat

Mehrdad Mohammad H Reshadi

Sudha Anil Kumar Gathala

Michael P Mahan

Mriganka Mondal

Kishore Kumar Pusukuri

Wendell Ruotsi

Shaizeen Aga

Michael Weber

Mona Mahmoudi

Vikram Mandyam

Ravish Hastantram

Chettan S Dhillon

Mehrdad H Reshadi

Adrian L D Sampson

Rajiv Vijayakumar

Maurice Ribble

Mohammed H Reshadi

Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states.

Method and apparatus for optimized execution using resource utilization maps

Aspects include computing devices, systems, and methods for implementing scheduling and execution of lightweight kernels as simple tasks directly by a thread without setting up a task structure. A computing device may determine whether a task pointer in a task queue is a simple task pointer for the lightweight kernel. The computing device may schedule a first simple task for the lightweight kernel for execution by the thread. The computing device may retrieve, from an entry of a simple task table, a kernel pointer for the lightweight kernel. The entry in the simple task table may be associated with the simple task pointer. The computing device may directly execute the lightweight kernel as the simple task.

Method for simplified task-based runtime for efficient parallel computing

Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.

Identifying enhanced synchronization operation outcomes to improve runtime operations

Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

System and method for allocating memory to dissimilar memory devices using quality of service

Methods, and devices implementing the methods, use device-specific classifiers in a privacy-preserving behavioral monitoring and analysis system for crowd-sourcing of device behaviors. Diverse devices having varying degrees of 'smart' capabilities may monitor operational behaviors. Gathered operational behavior information may be transmitted to a nearby device having greater processing capabilities than a respective collecting device, or may be transmitted directly to an 'always on' device. The behavior information may be used to generate behavior vectors, which may be analyzed for anomalies. Vectors containing anomaly flags may be anonymized to remove any user-identifying information and subsequently transmitted to a remote recipient such as a service provider or device manufacture. In this manner, operational behavior information may be gathered about different devices from a large number of users, to obtain statistical analysis of operational behavior for specific makes and models of devices, without divulging personal information about device users.

Methods and systems for automated anonymous crowdsourcing of characterized device behaviors

Embodiments include computing devices, apparatus, and methods implemented by the apparatus for time varying address space layout randomization. The apparatus may launch first plurality of versions of a system service and assign a random virtual address space layout to each of the first plurality of versions of the system service. The apparatus may receive a first request to execute the system service from a first application. The apparatus may randomly select a first version of the system service from the first plurality of versions of the system service, and execute the system service using data of the first version of the system service.

Time varying address space layout randomization

Methods, servers, and systems for using signatures/certifications embedded in pre-processed code to enable use or reuse of pre-processed code to obviate the need to perform some operations or execute some scripts within the web page content. One or more operations may be performed within an executable script in web page content and signing the result of the operation in a manner that can be used to verify that the corresponding operation may be skipped by a browser. A browser receiving signed pre-processed code may use a signature verification process to determine whether the browser can bypass executing corresponding scripts in the web page content or perform alternative operations. Operations may be pre-performed and the results signed by off-line tools and included in the web page content. Results of operations may be stored in memory along with a signature so the results of the operation can be reused in the future.

Reducing web browsing overheads with external code certification

Aspects include apparatuses, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Hardware acceleration for inline caches in dynamic languages

Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.

Data management for multiple processing units using data transfer costs

Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Multi-processor computing device methods manage resource accesses by a signaling event manager signaling processor elements requesting access to a resource to wake up to access the resource when the resource is available or wait for an event when the resource is busy. Processor elements may enter a sleep state while awaiting access to the requested resource. When multiple elements are waiting for the resource, the processor element with a highest assigned priority is signaled to wake up when the resource is available without waking other elements. Priorities may be assigned to processor elements waiting for the resource based on a heuristic or parameter that may depend on a state of the computing device or the processor elements. A sleep duration may be estimated for a processor element waiting for a resource and the processor element may be removed from a scheduling queue or assigned another thread during the sleep duration.

Directed event signaling for multiprocessor systems

Embodiments include computing devices, systems, and methods for task-based handling of repetitive processes in parallel. At least one processor of the computing device, or a specialized hardware controller, may be configured to partition iterations of a repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. Upon completing a task, remaining divisible partitions of the repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task or a newly initialized task. Information about the iteration space for a repetitive process may be stored in a descriptor table, and status information for all partitions of a repetitive process stored in a status table. Each processor core may have an associated local table that tracks iteration execution of each task, and is synchronized with the status table.

Method for exploiting parallelism in task-based systems using an iteration space splitter

The various aspects provide methods, servers, and systems for identifying independent portions of an HTML document so that the identified portions may be processed in parallel. The independent portions may be associated with an iframe tag having both the seamless and sandbox attributes. At runtime, a browser may detect the presence of both attributes, and process the contents of the iframe in parallel.

HTML5 I-frame extension

Methods and devices for accelerating webpage rendering by a browser store document object model (DOM) tree structures and computations of rendered pages, and compare portions of a DOM tree of pages being render to determining if portions of the DOM tree structures match. If a DOM tree of a webpage to be rendered matches a DOM tree stored in memory, the computations associated with the match DOM tree may be recalled from memory, obviating the need to perform the calculations to render the page. A tree isomorphism algorithm may be used to recognize DOM trees stored in memory that match the DOM tree of the webpage to be rendered. Reusing rendering computations may significantly reducing the time and resources required for rendering web pages. Identifying reusable portions of calculation results based on DOM tree isomorphism enables the browser to reuse stored webpage rendering calculations even when URLs do not match.

Memoizing web-browsing computation with DOM-based isomorphism

Growing community of inventors

Palo Alto, CA, United States of America

Gheorghe Calin Cascaval