International Business Machines Corporation

Ghazi Sarwat Syed

Abu Sebastian

Benedikt J Kersting

Manuel Le Gallo-Bourdeau

Vara Sudananda Prasad Jonnalagadda

Timothy Mathew Philip

Timoleon Moraitis

Benedikt Kersting

Urs Egger

Photonic content-addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter device is selectively programmable in first and second states representing respective stored bit values that filters out light according to the programming. An encoder for encoding a plurality of input bit-strings into optical signals such that bit values in different bit-strings are encoded using optical signals in different pairs of optical states, and to simultaneously supply the optical signals corresponding to each bit-position in the bit-strings to a respective row waveguide of the array. The CAM further comprises a detector for detecting light in any of said optical states in each column waveguide, thereby identifying any mismatch between each input bit-string and bit values stored in the filter devices coupling light to that waveguide.

Photonic content-addressable memory and applications thereof

Systems and methods for modulating conductance of a plurality of unit cells are described. A controller can determine a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory devices. The plurality of conductance values can be less than maximum conductance values of the plurality of unit cells. The controller can determine a read gate voltage for driving a plurality of access transistors to read from connected to the plurality of unit cells under a read operation. The controller can map a plurality of weights to the plurality of conductance values and to the read gate voltage.

Conductance modulation in computational memory

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

Solving optimization problems with photonic crossbars

The invention is notably directed to a device comprising a plurality of resistive memory elements. The plurality of resistive memory elements comprises a resistive material. The device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to perform a temporary resistance change of the resistive material of the subset for a predefined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that a resistance of the subset of the plurality of resistive elements reverts automatically during the predefined retention period from the second resistance state to the first resistance state by an inherent material property of the resistive material, thereby automatically deleting the second binary state.

Device with reconfigurable short term data retention

Configurable sensor units and sensor apparatus are provided. A configurable sensor unit comprises a sensor device for generating an electrical signal, dependent on a stimulus sensed by the device, in a circuit, and a programmable non-volatile memory element operable in the circuit as a load resistor for the sensor device, whereby resistance of the load resistor depends on a programmed state of the memory element. The sensor unit has an output for providing an output signal dependent on the aforementioned electrical signal and programmed state. Sensor apparatus may comprise a plurality of these configurable sensor units. Such sensor apparatus may be configured to perform in-sensor compute operations for neural network architectures. Further sensor apparatus comprises a configurable sensor unit and a controller for programming the memory element of the sensor unit to a programmed state dependent on an operating requirement for the sensor unit.

Configurable sensor units and sensor apparatus

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.

Device for matrix-vector multiplications

A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Projected memory device with carbon-based projection component

A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Projected memory device with reduced minimum conductance state

A neuromorphic memory element comprises a memristor, a plurality of the neuromorphic memory elements and a method for operating the same may be provided. The memristor comprises an input signal terminal, an output signal terminal, and a control signal terminal, and a memristive active channel comprising a phase change material. The memristive active channel extends longitudinal between the input signal terminal and the output signal terminal, and a control signal voltage at the control signal terminal is configured to represent volatile biological neural processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal is configured to represent non-volatile biological neural processes of the neuromorphic memory element.

Multi-terminal neuromorphic device

A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved.

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Zurich, Switzerland

Ghazi Sarwat Syed