Semiconductor Insights Inc.

Ghassan Naim

George Chamberlain

Larry Lam

John-Scott Thomas

Alexei Ioudovsky

Alexi Ioudovski

A method for analyzing an integrated circuit (IC). At least a portion of a layer of the IC is scanned using high magnification, to obtain images of the IC. The images are registered to create a mosaicked image. An IC layout database is created in the form of a set of polygons from the mosaicked image, where the step of creating the IC layout database is performed after, or pipelined with, the registering step. The process is repeated for plural IC layers, as necessary. Polygon sets from each layer are vertically registered into alignment with minimal distortion. A netlist or schematic diagram is generated to represent the scanned IC portion based on the registered set(s) of polygons.

Method to extract circuit information

A method of analyzing at least a portion of an integrated circuit (IC) comprised of the steps of automatically: (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes, (b) extracting features of interest from the first digital signals to provide second digital signals representing values of groups of pixels defining the features of interest, (c) modifying the second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of the layer, (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of the layers are provided, (e) registering the plural third signals relative to each other so as to represent vertical alignment of the layers by determining features of interest representative of IC mutual interconnection locations between layers, and using the locations as control points for the registering, and establishing an integrated circuit layout database therefrom, (f) generating a netlist from data signals defining the cells, and (g) generating a schematic diagram of a circuit contained in the integrated circuit from the netlist.

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Ghassan Naim