Intel Corporation

Ghassan Khadder

Gregory Scott Mathews

Judge K Arora

Michael J Morrison

Harshvardhan P Sharangpani

Bharadwaj Pudipeddi

Josef R Call

Sreenivas A Reddy

In one embodiment, the present invention includes a method for receiving a request for data in a home agent of a system from a first agent, prefetching the data from a memory and accessing a directory entry to determine whether a copy of the data is cached in any system agent, and forwarding the data to the first agent without waiting for snoop responses from other system agents if the directory entry indicates that the data is not cached. Other embodiments are described and claimed.

Avoiding snoop response dependency

A computer product, method, and apparatus for causing a computer to perform load operations in a particular way are disclosed. The computer is made to replace a load instruction at a particular location in a computer program instruction sequence with two instructions, an advanced load instruction and a load check instruction. The advanced load instruction is inserted into the instruction sequence up-stream from where the original load instruction was located, and may be inserted above store instructions. The load check instruction is inserted into the instruction sequence after the store instructions. An Advanced Load Address Table (ALAT) structure, containing physical address data and validity data for each non-speculative advanced load, is updated with data about each advanced load and each store instruction executed, and queried on execution of each load check instruction about whether or not a particular advanced load is safe to use. An advanced load speculative pipeline and speculative invalidation pipeline are similarly queried regarding speculative advanced loads.

Method and apparatus for advancing load operations

In one method, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.

Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stall

A method and apparatus for detecting address range overlaps. According to one embodiment, a first mask is generated for a first address range and a second mask is generated for a second address range. A first AND operation is performed on the first address range and the second mask to output a first temporary value. A second AND operation is performed on the second address range and the first mask to output a second temporary value. The first temporary value is then compared to the second temporary value to detect an overlap between the first address range and the second address range. According to an alternate embodiment, a first mask is generated for a first address range and a second mask is generated for a second address range. The first mask is then compared to the second mask to detect an overlap between the first address range and the second address range.

Method and apparatus for detecting address range overlaps

A cache controller for a set associative cache selectively remaps predetermined bits of the cache address so as to confine data from a single memory page to a particular block of the cache memory. When changing a memory page, only the particular block of the cache in which data from that page may be stored is flushed, thereby preserving the remaining contents of the cache.

Growing community of inventors

San Jose, CA, United States of America

Ghassan Khadder