International Business Machines Corporation

Ghadir Robert Gholami

Diane Garza Flemming

William A Maron

Mysore Sathyanarayana Srinivas

Mark David McLaughlin

Octavian Florin Herescu

John Daniel Upton

Chetan Mehta

Khuong Huu Pham

Jorge N Yanez

A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.

Managing thermal condition of a memory

A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

Bus access moderation system

A multi-chip module (MCM) assembly has two modules interconnected by respective interposers and a printed circuit board, and diagnostic logic within the modules uses the principal of signal reflection to located any open fault in the circuit path across the interposers. A first test signal is sent from module to the other and a determination is made as to whether any reflected signal represents an open fault of the circuit path at either of the interposers. If a reflected signal is received during a predetermined time, the diagnostic logic concludes that a single open fault exists only at the far interposer. If no reflected signal is received then the diagnostic logic concludes that there is at least one open fault at the near interposer, and the second module runs a similar test to check to see if both interposers have failures.

Method to improve isolation of an open net fault in an interposer mounted module

A modified system causes the REQ64&num; signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64&num; signal low. This will synchronize reset and REQ64&num;, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.

System solution to allow 64-bit PCI adapters to determine state during reset

A method and system for servicing an interrupt is presented. An interrupt handler associated with a detected interrupt is invoked, and a determination is made as to whether to instantiate a delay before further servicing of the detected interrupt. If a delay is neccesary before the detected may be fully serviced, a delay counter is initialized to a first predetermined value. The interrupt handler then exits without fully servicing the detected interrupt. During subsequent invocations, the interrupt handler decrements the delay counter and checks whether the delay counter has reached a second predetermined value. The interrupt handler is repeatedly invoked while the interrupt remains pending and while the delay counter does not equal the second predetermined value, the interrupt handler may then fully service the interrupt and clear the interrupt.

Method for determining if a delay required before proceeding with the detected interrupt and exiting the interrupt without clearing the interrupt

An electronic system, precharge circuit, and method for precharging system net. The system includes a plurality of devices. Each of the devices includes at least one I/O pin driven by an driver circuit. The system further includes a system net connected to at least one of the I/O pins of each of the plurality of devices. A precharge circuit suitable for connecting to the system net is provided. The precharge circuit includes a sense stage and a charging stage. The sense stage is configured to receive the system net voltage as an input and adapted to sense a system net voltage transition. The charging stage is connected to the system net and configured to receive an output of the sense stage. The sense stage is configured to activate the charging stage in response to detecting a system net voltage transition. The charging stage, upon activation, is configured to provide a current path between a supply voltage and the system net for a specified duration. After the specified duration, the current path is disabled.

Circuit for rapidly charging a system net

An active circuit for rapidly discharging stored energy in a capacitive system. The circuit is comprised of a variable impedance circuit, a voltage detector, and a time delay circuit. The variable impedance circuit includes a variable impedance output path configured to be connected between a Vcc bus of the capacitive system and ground. The voltage detector circuit includes an input coupled to the Vcc bus and an output connected to an input of the variable impedance circuit. The voltage detector circuit is configured to maintain the variable impedance output path in a high impedance condition while the Vcc voltage remains above a predetermined minimum value. The time delay circuit is coupled to the input of the variable impedance circuit and configured to maintain the variable impedance output path in a low impedance condition for a duration after the voltage of the Vcc bus drops below the predetermined minimum.

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Austin, TX, United States of America

Ghadir Robert Gholami