Samsung Electronics Co., Ltd.

Geunwoo Kim

Wandon Kim

Yoon Tae Hwang

Heonbok Lee

Hyunbae Lee

Yoontae Hwang

Sunjung Lee

Jungmin Park

Taegon Kim

Minwoo Song

Hanki Lee

Namgyu Cho

Kughwan Kim

Changhyun Kim

Namjun Cho

Seunghee Lee

Hyun Cheol Kim

Soojae Park

Jongyoub Ryu

Youngjun Park

Jiwon Shin

Donguk Kwon

Jeonghyuk Yim

Ohchul Kwon

WooRam Myung

Hyunwoo Kang

Sangmin Jung

Sangho An

Keunho Jang

Kwangbok Woo

Byoungkab Choi

Hyesun Yoon

Seonju Oh

Soohoon Lee

Towhidul Islam

Muhammad Mushfiqul Islam

Md Imtiaz Hossain

Younjo Mun

Yun-Sik Yoo

A semiconductor device includes; a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, wherein the channel pattern is connected to the source/drain pattern, a gate electrode on the channel pattern, and a gate contact connected to a top surface of the gate electrode, wherein the gate contact includes a capping layer directly contacting the top surface of the gate electrode and a metal layer on the capping layer, wherein the capping layer and the metal layer include the same metal, a concentration of oxygen in the metal layer ranges from between about 2 at % to about 10 at %, and a maximum concentration of oxygen in the capping layer ranges from between about 15 at % to about 30 at %.

Semiconductor device and method of fabricating the same

Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

Semiconductor package and method of manufacturing the semiconductor package

An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

Integrated circuit device

A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

Semiconductor device

An electronic device includes a first communication module, a second communication module, a display, a processor, and a memory storing instructions causing the processor to receive, from an external electronic device connected via the first communication module, first data related to a first screen on which resources of the external electronic device are configured in accordance with a graphic environment of the electronic device, output the first screen on the display, request the external electronic device to execute a selected first resource, receive, from the external electronic device, a request for obtaining second data related to the first resource, connect to the network via the second communication module to obtain the second data, transmit the obtained second data to the external electronic device, receive, from the external electronic device, third data related to a second screen configured using the second data, and output the second screen on the display.

Network connection method and electronic device supporting same

A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Method of manufacturing a semiconductor device

A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

Method of fabricating a semiconductor device

A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

Provided is an electronic apparatus. The electronic apparatus includes an audio receiver configured to obtain an audio signal of sound output by an external object; a sensor configured to sense a posture of the electronic apparatus; a display; and a processor configured to, based on the audio signal that is obtained by the audio receiver, determine a direction in which the external object is located with respect to the electronic apparatus, and control the display to display a graphical object that corresponds to the external object based on the posture of the electronic apparatus sensed by the sensor and the direction in which the external object is located.

Electronic apparatus, controlling method of electronic apparatus and computer readable medium

A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

An electronic device comprises a plurality of antennas, wherein each of the plurality of antennas are spaced apart from each other, a first communication circuit electrically connected with the plurality of antennas, a plurality of array antennas comprising a first array antenna disposed adjacent to at least one of the plurality of antennas, and a second array antenna disposed adjacent to another antenna different from the at least one antenna of the plurality of antennas, a second communication circuit electrically connected with the first array antenna and the second array antenna, and at least one control circuit electrically connected with the first communication circuit and the second communication circuit, wherein the at least one control circuit is configured to obtain receive sensitivities of the plurality of antennas through the first communication circuit; activate at least one array antenna of the first array antenna and the second array antenna through the second communication circuit based at least on the receive sensitivities; and control the activated at least one array antenna to form at least one beam for communication with an external electronic device.

Electronic device including antenna module

A semiconductor package may include a package substrate, a molded interposer package (MIP) and a first stiffener. The MIP may be arranged on the package substrate. The MIP may include an interposer, at least one first semiconductor chip and at least one second semiconductor chip molded by a molding member. The first stiffener may be attached to any one of outer surfaces of the MIP. The first stiffener may be spaced apart from the upper surface of the package substrate to suppress a warpage of the MIP. Thus, central conductive bumps between the MIP and the package substrate may not be upwardly floated to improve an electrical connection between the central conductive bumps and the package substrate. Further, a short between edge conductive bumps between the MIP and the package substrate may not be generated.

Semiconductor package

A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

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Seoul, South Korea

Geunwoo Kim