Samsung Electronics Co., Ltd.

Geun Won Lim

Seok Cheon Baek

Jun Hyoung Kim

Kwang Soo Kim

Joong Shik Shin

Young-Jin Kwon

Ji Sung Cheon

Bong Hyun Choi

Jong Woo Shin

Seung Min Song

Jun Hui Kim

Yong Jin Kwon

Kang Min Kim

Beyoung Hyun Koh

A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Vertical memory device

A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Method of fabricating a semiconductor memory device including an extension gate cutting region

A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

Semiconductor memory devices, methods for fabricating the same and electronic systems including the same

Semiconductor device including a cell array region and an extension region

A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

Semiconductor device including a cutting region having a height greater than a height of a channel structure

A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

Nonvolatile memory device with h-shaped blocks and method of fabricating the same

A nonvolatile memory device and a method of fabricating a nonvolatile memory device, the device including a substrate; a first mold structure on the substrate, the first mold structure including a plurality of first mold insulation films and a plurality of first gate electrodes, which are alternately stacked; a channel structure that penetrates the first mold structure and intersects the plurality of first gate electrodes; and at least one insulation filler that intersects the plurality of first mold insulation films and the plurality of the first gate electrodes, wherein the first mold structure is electrically separated by a word line cutting region extending in a first direction such that the first mold structure includes a first block region and a second block region, and the at least one insulation filler is in the word line cutting region and connects the first block region and the second block region.

Nonvolatile memory device and method of fabricating the same

A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Semiconductor device including a peripheral circuit region and memory cell regions

A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.

Non-volatile memory device and method for fabricating the same

A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

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Yongin-si, South Korea

Geun Won Lim