Samsung Electronics Co., Ltd.

Geun-Soon Kang

Hee-Cheol Choi

Min-kyu Song

Seong-won Kim

Eu-Ro Joe

Seung-hoon Lee

Dong-young Chang

You-Mi Lee

Energy economized pass-transistor logic circuit and full adder using the

Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

CMOS operational amplifiers having reduced power consumption

A binary-weighted capacitor array is applicable for use in analog-to-digital or digital-to-analog converters, switched-capacitor filters, etc. A plurality of unit capacitors are arranged in a lateral row. The row is laid out in parallel to a switch array so that each metal interconnect between a unit capacitor and a corresponding switch is of a uniform length. This layout eliminates several limitations commonly found in capacitor arrays, including: top-plate parasitic error due to metal interconnections and metal overlap; ratio error due to oxide thickness gradients; and edge-definition errors.

Switched-capacitor array

A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

CMOS output buffer circuit exhibiting reduced switching noise

Growing community of inventors

Kyunggi-do, South Korea

Geun-Soon Kang