Skhynix Inc.

Geun Il Lee

Soo Young Jang

Jung Hwan Ji

Kyu Bong Kong

Dae Han Kwon

Kyu Dong Hwang

Min Soo Park

Yong Suk Joo

Sung Yub Lee

Kyung Ho Chu

I Yeong Jung

Seung Bong Kim

A refresh circuit is configured to generate a counting signal by counting a refresh command and to generate a plurality of preliminary refresh cycle change signals by decoding the counting signal. The refresh circuit is also configured to change a refresh cycle based on one of the plurality of preliminary refresh cycle change signals and to perform a refresh operation.

Refresh circuit and semiconductor memory device including the same

A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Clock distribution circuit and semiconductor device including the clock distribution circuit

A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Semiconductor apparatus related to receiving clock signals having variable frequencies, and system including the semiconductor apparatus

A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Semiconductor apparatus and test system including the semiconductor apparatus

A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.

Operation control circuit and semiconductor memory device including the operation control circuit

A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.

Semiconductor apparatus capable of improving efficiency for a circuit configuration and a signal line interconnection

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.

Semiconductor apparatus

A semiconductor system is provided, which includes a controller configured to output an active command and test mode signals; and a semiconductor device configured to sense and amplify a pair of bit lines by generating a first power control signal of which a pulse width is adjusted in accordance with a combination of the test mode signals during an enable period of an enable signal generated by the active command, receiving a supply of a first power according to the first power control signal, and receiving a supply of a second power according to a second power control signal.

Semiconductor device and semiconductor system

A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.

Clock generation circuit and clock generation system using the same

An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an update pulse signal, a control unit configured to determine whether the impedance control signal is within a predetermined range and generate an update enable signal according to a determination result, and a prohibition unit configured to control input of the update pulse signal to the storage unit in response to the update enable signal.

Growing community of inventors

Yongin-si, South Korea

Geun Il Lee