Hynix Semiconductor Inc.

Skhynix Inc.

Geun-Il Lee

Chang-Kyu Choi

Sung-Yub Lee

Jae-Hoon Cha

Yong-Suk Joo

Jung-Hwan Ji

Yong-suk Joo

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

Semiconductor memory device for performing refresh operation and operating method therof

A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.

Semiconductor memory device for performing both of static test and dynamic test during wafer burn-in test and method for operating the same

Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data.

Semiconductor memory device and semiconductor system including the same

A data transferring circuit includes a data transferor configured to transfer data through a plurality of parallel data transfer lines, wherein the data transferor is further configured to partially invert the transferred data in response to an inversion signal, and a pattern sensor configured to enable the inversion signal when data transferred through the parallel data transfer lines is to cause three sequential lines to transfer data of a logic value through a middle one of the sequential lines and data of an inverse of the logic value through the remaining ones of the sequential lines or cause all of the transfer lines to transfer data of a same logic value.

Data transferring circuit and data transferring/receiving system

A data transmission/reception system includes a data transmission circuit and a data reception circuit. The data transmission circuit includes a pattern detection unit configured to detect a pattern of data to be loaded on inner lines among a plurality of transmission lines and generate an inversion signal, and a transmission unit configured to transmit data to the plurality of transmission lines and the inversion signal to an inversion line, and invert some of the data to be loaded on the inner lines in response to the inversion signal. The data reception circuit is configured to invert the data inverted by the transmission unit among the data transferred to the plurality of transmission lines, in response to the inversion signal.

Data transmission circuit and data transmission / reception system

A semiconductor device may include an internal circuit configured to perform write operations in response to each of a plurality of write commands, wherein the plurality of write commands are sequentially input to the internal circuit, a first pulse generation unit configured to generate a first pulse activated during a first delay amount in response to a write command, a second pulse generation unit configured to generate a second pulse activated during the first delay amount in response to a delayed write command out of the plurality of write commands after a second delay amount from the activation time of the first pulse, and a transfer control unit configured to prevent commands other than the plurality of write commands from being transferred to the internal circuit during a sum of the activation period of the first pulse and the activation period of the second pulse.

Semiconductor device and operation method thereof

An on-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response to the calibration code; and a reference resistor unit coupled to the calibration resistor unit, and configured to be turned on and off in response to a control signal.

On-die termination device

A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate a first process signal, a first clock termination unit configured to be coupled with a first clock path and determine an impedance value responding to the impedance control signal, and a second clock termination unit configured to be coupled with a second clock path and determine an impedance value responding to the first process signal.

Semiconductor device

A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal.

Semiconductor memory apparatus

A data output circuit includes a plurality of drivers configured to be turned on/off according to impedance codes to output data to an output node. The impedance codes are divided into a first group having a value to turn on the drivers, and a second group having a value to turn off the drivers, and at least some of the drivers controlled by the second group are turned on during a pre-emphasis period.

Data output circuit

A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.

Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus

An impedance matching device includes a calibration circuit configured to generate impedance calibration codes for modification of impedance; a code modification unit configured to modify the impedance calibration codes according to impedance setting information and output modified impedance calibration codes; and a termination impedance unit configured to terminate an interface node with impedance determined according to the modified impedance calibration codes.

Termination circuit and impedance matching device including the same

A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.

Parallel-to-serial converting circuit

A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

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Gyeonggi-do, South Korea

Geun-Il Lee