Skhynix Inc.

Lg Electronics Inc.

Geun Ho Choi

Woongrae Kim

Min Su Park

Kyung Mook Kim

Myung Kyun Kwak

Sun Myung Choi

Dong Kyun Kim

Seung Wook Oh

Jin Il Chung

Man Keun Kang

Min Gyu Park

Yong Ho Kim

Dong Uk Lee

Tae Yong Lee

Jae Il Kim

Hyeong Soo Jeong

Ki Hun Kwon

Han Kyu Chi

Yong Suk Joo

Young Hyun Baek

Ho June Kim

Doo Hwan Myung

An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Electronic device for controlling command input

A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.

Shift register and electronic device including the same

A semiconductor system includes a controller configured to output a clock, a command and an address; and a semiconductor device configured to generate a flag signal by detecting an input time of the command, which is input in synchronization with the clock in a write auto-precharge operation based on the command, and configured to generate an internal address for performing the write auto-precharge operation, by serializing the address and then parallelizing the flag signal and the serialized address.

Semiconductor device and semiconductor system performing auto-precharge operation

A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Semiconductor device for performing an error check operation

A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.

System for performing a phase control operation

A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.

Semiconductor devices controlling column operation of banks

A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.

System for performing phase matching operation

A shift register includes a latch clock generation circuit and a clock latch circuit. The latch clock generation circuit generates a latch clock signal and an inverted latch clock signal based on a first internal clock signal, a first inverted internal clock signal, a second internal clock signal, and a second inverted internal clock signal. The clock latch circuit latches a control signal in synchronization with one signal selected from the first internal clock signal, the first inverted internal clock signal, the second internal clock signal, and the second inverted internal clock signal. The clock latch circuit also latches the latched control signal in synchronization with the latch clock signal or the inverted latch clock signal to generate and output a shift control signal.

Shift registers

A semiconductor device includes a flag shifting circuit and an auto-pre-charge control circuit. The flag shifting circuit generates a first shifted flag signal by shifting a first flag signal by a second latency period, the first flag signal generated based on a first operation clock signal, and configured to generate a second shifted flag signal by shifting a second flag signal by a first latency period, the second flag signal generated based on a second operation clock signal. The auto-pre-charge control circuit generates an auto-pre-charge signal by shifting the first shifted flag signal and the second shifted flag signal by a recovery period based on the first operation clock signal and the second operation clock signal.

Semiconductor devices

A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Command generation method and semiconductor device related to the command generation method

A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.

A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

Fail redundancy circuits

A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

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Icheon-si, South Korea

Geun Ho Choi