Qimonda Ag

Qimonda Flash Gmbh

Gert Koebernik

Detlev Richter

Jan Gutsche

Christoph Friederich

Josef Willer

Michael Specht

Dirk Manger

Girolamo Gallo

Klaus Knobloch

Steffen Meyer

Michael Scheppler

Roberto Ravasio

Ramirez Xavier Veredas

Mirko Reissmann

Eike Ruttkowski

Holger Moeller

Doris Keitel Schulz

Joseph Willer

Kenny Oisin

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.

Integrated circuits having a controller to control a read operation and methods for operating the same

Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.

Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.

Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

Growing community of inventors

Unterhaching, Germany

Gert Koebernik