Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Imec Vzw

Gert Claes

Simone Severi

Ann Witvrouw

John Heck

Luc Haspeslagh

Bin Guo

Ajay Jain

Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti&#x2014;TiN interlayer in the anchor region may be added. The ratio of the total SiGe&#x2014;SiGe anchor area to the SiO&#x2014;SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

Thin film wafer level package

A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Method of manufacturing a semiconductor device and semiconductor devices resulting therefrom

The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Method for forming MEMS devices having low contact resistance and devices obtained thereof

Growing community of inventors

Kessel-lo, Belgium

Gert Claes