Intel Corporation

Juniper Networks, Inc.

Northern Telecom Limited

Duke University

Mcnc

Astarix Inc.

Gershon Kedem

Ronny Ronen

Spencer H Greene

Adi Yoaz

Mark D Kellam

Franc Brglez

Clay S Gloster, Jr

Thomas Alexander

A system and method form searching an associative memory using input key values and first and second hashing sections. Key values (Kn) can be hashed in the first hashing section ( ) to generate first output values H (Kn) that access a first store ( ). The first store or memory portion ( ) can include &ldquo;leaf&rdquo; pointer entries ( - ) and &ldquo;chunk pointer&rdquo; entries ( - ). A leaf pointer entry ( - ) points at data associated with an applied key value. A chunk pointer entry ( - ) includes pointer data. If a chunk pointer entry ( - ) is accessed, the key value (Kn) is hashed in the second hashing section ( ) to generate second output values H (Kn) that access a second store or memory portion ( ). Second hashing section ( ) hashes key values (Kn) according to selection data SEL stored in a chunk pointer entry ( - ). The system may also include a first memory portion accessed according to address values from the first hashing section and a second memory portion accessed according to address values that include outputs from the second hash section and a chunk base address value. The hash based associative system allows for the selection of a second hash function that has been precomputed at table build time to be perfect with respect to a small set of colliding key values, provides a deterministic search time independent of the number of table entries or width of the search key, and allows for pipelining to achieve highest search throughput.

System and method for searching an associative memory utilizing first and second hash functions

A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier. At least one prefetch candidate is generated based on the memory request and the access history.

Method and apparatus for cache line prediction and prefetching using a

Predictive cache memory systems and methods are responsive to cache misses to prefetch a data block from main memory based upon the data block which last followed the memory address which caused the cache miss. In response to an access request to main memory for a first main memory data block, which is caused by a primary cache miss, a second main memory data block is identified which was accessed following a previous access request to the main memory for the first main memory data block. Once identified, the second memory data block is stored in a predictive cache if the second main memory data block is not already stored in the predictive cache. Thus, if the next main memory request is for the second main memory block, as was earlier predicted, the second main memory block is already in the predictive cache and may be accessed rapidly. The identification of data blocks for prefetching may be provided by a prediction table which stores therein identifications of a plurality of succeeding main memory data blocks, each of which was accessed following an access request to a corresponding one of a plurality of preceding main memory data blocks. The Prediction Table is updated if predictions are incorrect. The predictive cache may be implemented using on-chip SRAM cache which is integrated with a DRAM array so that transfers between the DRAM array and the predictive cache may occur at high speed using an internal buffer.

Predictive caching system and method based on memory access which

A photoresist (18) is exposed through a design-independent high resolution reticle (20), producing a high resolution image of exposed resist (18A). Photoresist (18) is exposed for the second time through a design-specific low-resolution reticle (24), exposing selected portions (18D) of previously unexposed resist. The remaining portions (18B) of previously unexposed resist form a design-dependent high resolution image. After development of photoresist (18), its unexposed portions (18B) are removed, producing openings (26) in photoresist (18), that can be transferred to underlying material (36), for example by etching openings in that underlying material (36), thereby transferring the design-dependent high-resolution image to it. Since the design-independent high resolution reticle (20) can be prefabricated ahead of time and used to produce many designs with different functions, the above double-exposure method is suitable for fabricating design-specific high resolution features, e.g., contacts (vias) between conducting layers, within time and at the approximate cost required to fabricate and process a low resolution image. Several variants of the basic method are possible.

High resolution mask programmable via selected by low resolution

A high precision weighted random pattern generation system generates any desired probability of individual bits within a weighted random bit pattern. The system includes a circular memory having a series of weighting factors stored therein, with each weighting factor representing the desired probability of a bit in the weighted random pattern being binary ONE. The random bits from a random number generator and a weighting factor are combined to form a single weighted random bit. The random bits and weighting factor are combined in a series of interconnected multiplexor gates. Each multiplexor gate has two data inputs, one being a bit from the weighting factor, the other being the output of the preceding multiplexor gate. The random number bit controls the output of the multiplexor. For example, when the control input (random bit) is high, the multiplexor output is the weighting factor bit. When the control input (random bit) is low, the multiplexor output is the output of the preceding multiplexor. The output of the final multiplexor gate in the series is the weighted bit.

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Chapel Hill, NC, United States of America

Gershon Kedem