Trw Limited

Northrop Grumman Systems Corporation

Gershon Akerling

James M Anderson

Thomas S Tighe

Karen E Yokoyama

Steven J Mass

Marijan D Grgas

Anthony L Long

Mansoor K Siddiqui

Chunbo Zhang

Patty P Chang-Chien

William Roland Deal

Kevin M Leong

Kelly Jill Hennig

Peter Ngo

Eric L Upton

James M Murduck

Moshe Sergant

John W Spargo

Benjamin Tang

A method of making an electrical structure having a foam housing is set forth. The foam housing includes an interior surface forming a conductive cavity adapted to carry energized waveforms therethrough. An electrical component of the electrical structure is integrally formed with the interior surface as the foam housing of the structure is assembled. The method includes the steps of depositing a plating material into a mold, pouring a foam polymer into the mold and removing the plated foam structure from the mold without etching the section from the mold. The method further includes steps of forming a metallic form into a planar structure, filling the open pores of the foam with a material such as photo-resist, machining a cavity from the foam, electroplating the cavity in the foam then removing the photo-resist material.

Method of making a low mass foam electrical structure

A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield. The method and apparatus are used to implement a micro-integrated Focal Plane Array (mFPA) technology used for sub millimeter wave (SMMW) cameras, although many other applications are possible. MMICs of different technologies may be integrated into the same micromachined package thus achieving the same level of technology integration as in multi-wafer WLP integration.

Waveguide and semiconductor packaging

An electrical structure having a foam housing is set forth. The foam housing includes an interior surface forming a conductive cavity adapted to carry energized waveforms therethrough. An electrical component of the electrical structure is integrally formed with the interior surface as the foam housing of the structure is assembled.

RF transmission line disposed within a conductively plated cavity located in a low mass foam housing

A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.

Method for packaging integrated circuit chips

A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.

High performance vias for vertical IC packaging

A packaged die ( ) for an integrated circuit ( ) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit ( ) is still in a wafer format. A wafer substrate ( ) on which the integrated circuits ( ) have been fabricated is patterned and etched to form signal and ground vias ( ) through the substrate ( ). A back-side ground plane ( ) is deposited in contact with the ground vias ( ). A protective layer ( ) is formed on the top surface ( ) of the substrate ( ), and a protective layer ( ) is formed on the bottom surface ( ) of the substrate ( ), where the bottom protective layer ( ) fills in removed substrate material between the integrated circuits ( ). Vias ( ) are formed through the bottom protective layer ( ), and the wafer substrate ( ) is diced between the integrated circuits ( ).

High power chip scale package

The chip-to-board (or chip-to-MCM) connection assembly and method therefor features a semiconductor chip (,) having a front surface (,) on which external terminal pads are provided; a board or MCM (,) having a surface (e.g., a recessed surface) at a first side thereof to which the rear surface (,) of the chip is affixed; and a connection carrier (,), disposed as an overlay, which electrically links the chip and the board or MCM. In this assembly scheme, the connection carrier (e.g., a bump carrier) which is affixed to both the chip and the board or MCM, contains all required signal line tracings (,) to provide the electrical interconnection between the semiconductor chip and the board or MCM. The bump carrier replaces all bond wires (,) and the like and can include support/control circuitry, passive and/or active, associated with, for example, high-speed/high-power IC chips (,). The connection carrier (,) is provided with the electrical contacts (,) such as bump electrodes each interconnecting a contact location (,) at the surface side of the connection carrier facing the semiconductor chip and the oppositely disposed (i) external pad on the chip or (ii) external pad or landing (,) at a side of the board (,) facing the connection carrier (,). Heat generated during operation is released through the rear side of the semiconductor chip (,), which is affixed to the board or MCM (,).

Chip-to-board connection assembly and method therefor

A method for forming high frequency connections between a fragile chip and a substrate is described, wherein metal is selectively deposited on a surface of a chip and a surface of a substrate, and corresponding patterns of electrically conductive bumps are selectively evaporated on the surface of the chip and the surface of the substrate over the metal layers, to form a pattern of electrically conductive bumps having spongy and dendritic properties, placing the chip in aligned contact with the substrate where each electrically conductive chip bump mates with each corresponding electrically conductive substrate bump, and selectively applying heat and pressure to the chip and substrate causing each chip bump to fuse together with each corresponding substrate bump to form an electromechanical bond.

Method for forming high frequency connections to high temperature superconductor circuits and other fragile materials

A method and apparatus for bonding a chip to a substrate is described, wherein the apparatus includes a chip holder assembly comprising an outer holder having a cavity formed therein and an inner holder for holding the chip, and by releaseably securing the inner holder within the outer holder cavity and contacting the chip to the substrate the inner holder has selective angular rotation within the cavity to make parallel the chip and the substrate.

Method for parallel alignment of a chip to substrate

The invention relates to a method for producing an electrical connection to a high temperature superconductor (HTS) circuit, where a polymer material is applied to the HTS surface covering the circuit contact disposed on one surface of the HTS circuit, a via is created in the polymer material exposing the circuit contact, a diffusion barrier is applied into the via covering the circuit contact; and, a solder bump is applied to the diffusion barrier.

Process of fabricating high frequency connections to high temperature

Shielded stripline multi-lead flex cable is successfully attached to solder pads on a circuit board by applying a hot bar to the backside of the cable placed in abuttment with the associated solder pads. The hot bar generates sufficient heat to reflow pretinned cable elements and the corresponding solder pads of the circuit board. An attachment is attained in which the outer ground plane metal layer of the cable covers the signal lines and the other ground plane metal layer is attached adjacent those signal lines, producing effective RF shielding of the signal leads and minimizing introduction of inductance into the ground current circuit. A novel cable end configuration and cable termination is disclosed to implement the attaching procedure.

Stripline flexible cable to printed circuit board attachment system

A reworkable cold welded microelectronic multi-chip module contains cold welded microelectronic chips in which the chip's cold weld metal bonding pads (3) are constructed of a metal having one hardness and the corresponding cold weld metal bonding pads of the multi-chip module's substrate (5) are of a different greater hardness, which, despite the difference in hardness, cold weld to one another. Two forms of Indium preferably serve as the metals. If for any reason the chip must be removed from the module, it is found that the cold weld breaks at a predictable location. A new microelectronic chip may thereby be cold welded to the module substrate as a replacement. New rework and testing procedures are thereby made possible.

Growing community of inventors

Culver City, CA, United States of America

Gershon Akerling