Array Microsystems, Inc.

Samsung Electronics Co., Ltd.

Gerry C Lui Kuo

Thomas G Kopet

Stephen D Lew

Surendar S Magar

Michael E Fleming

Raul A Aguilar

Bradford G Taylor

The present invention provides an image compression/decompression coprocessor which is integrated on a single chip. The control bus has a control unit which is connected by an internal, global bus to a number of different, special purpose processing units. Each of the processing units is specifically designed to handle only certain steps in compression and decompression processes.

Image compression coprocessor with data flow control and multiple

A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Motion estimation coprocessor

A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units. The control apparatus permits the digital signal processing device and associated memory units to operate in a normal mode where a predetermined processing operation is performed on the members of a signal array, a recursive mode where a series of operations are performed on a signal array by a single digital signal processing unit, and a sequential mode where a series of processing operations are performed on a signal array using a by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in the signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.

Apparatus and method for flexible control of digital signal processing

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Colorado Springs, CO, United States of America

Gerry C Lui Kuo