International Business Machines Corporation

Gerry Ashton

Tad Jeffrey Wilder

Toshiharu Saitoh

Kevin A Duncan

Terry D Keim

A shift register latch (SRL) () compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (). The SRL includes a master latch (), a slave latch () and a circuit element () connected between the scan clock tree and the master latch. The scan clock generates a clock signal () having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (') based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention

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Castleton, VT, United States of America

Gerry Ashton