Nxp B.v.

Koninklijke Philips Corporation N.v.

St-ericsson Sa

Gerrit Willem Den Besten

Erwin Janssen

Johannes De Wilde

Rodger Frank Schuttert

Franciscus Gerardus Maria De Jong

Madan Vemula

Bernd Uwe Gerhard Elend

Arnoud Pieter Van Der Wel

Geertjan Joordens

James Raymond Spehar

Peter Van Den Hamer

Marcello Ganzerli

Marcus Egbert Kole

Volker Timm

Tim Pontius

Bernardus Adrianus Cornelis Van Vlimmeren

Friedel Gerfers

Bernardus Martinus Johannes Kup

James Caravella

Albertus Jan Paulus Maria Van Uden

Marcellinus J M Pelgrom

Andreas Koellmann

Jingsong Zhou

Adrianus J Van Tuijl

Jim E Conder

Pavel Petkov

Jozef Lw Kessels

Niraj Kumar

Martijn Martinus Hendrikus Van Der Cruijsen

Rigor Hendrikus Lambertus Van Der Heijden

Arnoud P Van Der Wel

Adrianus J M Van Tuijl

A coding module for a transceiver, the coding module comprising circuitry configured to:

Coding module for a transceiver

The disclosure relates to a coding module for an Ethernet transceiver. The coding module may include circuitry configured to: receive data-signaling representative of one or more data words; encode the data-signaling into one or more DC-balanced words each having a DC-balanced-word-length; provide a prepended-word for a first transmission, where a length of the prepended-word is at least as long as the DC-balanced-word-length; and provide the one or more DC-balanced words for a second transmission, where the second transmission is subsequent to the first transmission. The coding module may include circuitry configured to: receive a prepended-word and provide a logic-high signal to an Energy Detect terminal; receive one or more DC-balanced words each having a DC-balanced-word-length; remove a DC-balanced coding from the one or more DC-balanced words to generate data signaling representative of one or more data words; and provide the data signaling to an output terminal.

Ethernet transceiver coding module

An apparatus for a local area network includes a management communications bus, and at one of a plurality of logic nodes, logic circuitry. The management communications bus is for communication among the plurality of logic nodes, wherein respective node addresses for the plurality of logic nodes are conveyed using the management communications bus. The logic circuitry communicates information in a data/address field of the communications protocol with another of the plurality of logic nodes with reference to a subset of the predetermined set of patterned data bits in the data/address field to synchronize the transactions.

Apparatuses and methods involving synchronization using data in the data/address field of a communications protocol

Methods for communications and of communication device involve determining a half-duplex communications mode for a communications device, and in response to determining the half-duplex communications mode for the communications device, disabling an echo canceller of the communications device and determining a time-division multiplex (TDM) communications schedule over a point-to-point communications link. In response to disabling the echo canceller and determining the TDM communications schedule over the point-to-point communications link, data transmission is conducted over the point-to-point communications link according to the TDM communications schedule without echo cancellation at the communications device. The TDM communications schedule specifies non-overlapping transmission time slots for different communications devices and a silent period for echo fade-out between consecutive transmission time slots of the non-overlapping transmission time slots.

Communications device and method of communications

Exemplary aspects are directed to transceivers interlinked in a communication system, for example, in respective circuit-based nodes installed in battery-operated vehicle or other apparatus. Representative of the communication system are a first transceiver and a second transceiver which communicate with one another over a communication link, with the first transceiver initiating a request over the link to the second transceiver. The second transceiver may receive the request and, for a period of time in response to receiving to the request, monitor the link to detect whether any further signaling on the link by the first transceiver indicates to accept the request. In certain other more specific examples, the above aspects are used as part of a handshake protocol to mitigate delays and related issues in coordinating timely actions associated with the request.

Transceiver-based handshake/power-reduction

Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves determining a time-division multiplex (TDM) communications schedule over an asymmetrical point-to-point link and at a communications device, transmitting or receiving data according to the TDM communications schedule over the asymmetrical point-to-point link. The TDM communications schedule specifies multiple non-overlapping transmission time slots for different communications devices and a silent period for echo fade-out between consecutive transmission time slots of the non-overlapping transmission time slots.

An example apparatus for a local area network. The apparatus includes, at one of a plurality of logic nodes, a plurality of ports and a plurality of shared registers. The plurality of shared registers have a port address table to provide configurable port-address assignments that identify respective ones of the plurality of ports. The apparatus further includes a management interface controller that communicates with the plurality of ports and accesses at least one register via a selected one of the ports, and in response configures or manages the port-address assignments within the port address table.

Apparatuses and methods involving managing port-address assignments

An apparatus in various embodiments is for use in a local area network and includes a discernment logic circuit and logic circuitry. The discernment logic circuit discerns whether a requested communications transaction received over the management communications bus from another of the logic nodes involves a first type of transaction or a second type of transaction, the second type of transaction having a plurality of commands associated with the requested communications transaction to convey respectively different parts of the requested communications transaction including an address part and a data part. The logic circuitry disables, in response to a reset of an address pointer in the one of the plurality of logic nodes and the requested communications transaction being the second type of transaction, the address pointer to mitigate a likelihood that the requested communications transaction is performed via the communication protocol while the address pointer for the second type of transaction is erroneous.

Apparatuses and methods involving disabling address pointers

An example apparatus includes a discernment logic circuit and logic circuitry. The discernment logic circuit discerns whether a requested communications transaction received over the management communications bus from another of the plurality of logic nodes involves a first type of transaction or a second type of transaction. The second type of transaction has a plurality of commands associated with the requested communication transaction to convey respectively different parts of the requested communications transaction including an address part and a data part. The logic circuitry accesses, in response to discerning that the requested communications transaction involves the second type of transaction, a register of the plurality of registers associated with the first type of transaction, wherein the plurality of registers associated with the first type of transaction are mapped into a set of addresses for the second type of transaction.

Apparatuses and methods involving first type of transaction registers mapped to second type of transaction addresses

An example an apparatus includes a register set, data access circuitry, and configuration circuitry. The register set includes at least one addressable register to store data and to manifest a side effect in response to the at least one addressable register being accessed. The data access circuitry accesses the register set, which may cause the side effect, and the configuration circuitry selectively disables the side effect.

Apparatuses and methods involving selective disablement of side effects caused by accessing register sets

An example apparatus includes a line driver and an interface circuit. The line driver has a plurality of source-series terminated (SST) driver segments including switching circuitry to selectively switch among at least three voltage-reference levels to drive an output node, common to each of the SST driver segments, in response to received digital signals by switching at a rate that is faster than a baud rate characterizing the received digital signals. The interface circuit drives a transmission link, in response to a drive signal at the output node, with an analog signal representing an oversampling of the received digital signals.

Apparatuses and methods involving a segmented source-series terminated line driver

A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

Circuits for correction of signals susceptible to baseline wander

Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

Speed improvement for a decision feedback equalizer

A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages.

Charge pump circuit

A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal.

Growing community of inventors

Eindhoven, Netherlands

Gerrit Willem Den Besten