Sandisk Technologies Inc.

Sandisk Corporation

Sandisk Il Ltd.

Western Digital Technologies, Inc.

Gerrit Jan Hemink

Ken Oowada

Xiang Yang

Yingda Dong

Shih-Chung Lee

Toru Miwa

Shinji Sato

Dana Lee

Deepanshu Dutta

Jeffrey W Lutze

Jun Wan

Masaaki Higashitani

Teruhiko Kamei

Christopher John Petti

Yupin K Fong

Henry Chin

Federico Nardi

Idan Alrod

Zhenming Zhou

Man Lung Mui

Mohan Dunga

Bo Lei

Guirong Liang

Eran Sharon

Jian Feng Chen

Tuan Duc Pham

Changyuan Chen

Tien-Chien Kuo

Tai-Yuan Tseng

Biswajit Ray

Chun-Hung Lai

Hao Fang Fang

Yan Li

Nima Mokhlesi

Peter Rabkin

Jianmin Huang

Steven Theodore Sprouse

Dengtao Zhao

Seungpil Lee

Won Ho Choi

Aaron Lee

Hao Nguyen

Anubhav Khandelwal

Geoffrey Steven Gongwer

Fanglin Zhang

Yee Lih Koh

Jong Park

Johann Alsmeier

James K Kai

Raul-Adrian Cernea

Huai-Yuan Tseng

Tong Zhang

Henry Chien

Daniel Lee Helmick

Wei Zhao

Martin Lueker-Boden

Minghai Qin

Sarath Chandran Puthenthermadam

Zhenyu Lu

Pi-Feng Chiu

Wen Ma

Arash Hazeghi

Wenguang Shi

Jianzhi Wu

Jiyin Xu

Xiaolong Hu

Lei Lin

Zhuojie Li

Koji Miyata

Bijesh Rajamohanan

Xiaochang Miao

Chandu Gorla

Shinjo Sato

Hironobu Nakao

Eron Sharon

An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.

Program dependent biasing of unselected sub-blocks

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

Non-volatile memory with sub-block based self-boosting scheme

Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

Reliability compensation for uneven NAND block degradation

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

Programming memory cells with concurrent redundant storage of data for power loss protection

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection

Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Concurrent programming of multiple cells for non-volatile memory devices

An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.

Vector matrix multiplication with 3D NAND

Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

Realization of binary neural networks in NAND memory arrays

The present disclosure generally relates to storage devices, such as solid state drives. A storage device comprises a controller comprising a controller error correction code (ECC) engine and a storage unit comprising a plurality of dies. Each of the dies comprise a die ECC engine. When user data is received, the controller ECC engine generates first ECC/error detection code (EDC) data. The user data and the first ECC/EDC data is sent to a die for storage as a code word. The die ECC engine generates second ECC/EDC data for the code word in granular portions. The second ECC/EDC data is used to correct bit errors in one or more code words up to a threshold value. When the number of bit errors exceeds the threshold value, the failed code words are sent to the controller ECC engine for correction.

Dual data protection in storage devices

A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Methods of forming a phase change memory with vertical cross-point structure

A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.

Non-volatile memory with countermeasure for over programming

An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

Bit line voltage control for damping memory programming

Growing community of inventors

Yokohama, Japan

Gerrit Jan Hemink