Nxp B.v.

Gerrit E J Koops

Erwin Hijzen

Raymond J E Hueting

Andreas Hubertus Montree

Michael A A In'T Zandt

Michael A A In 't Zandt

Jurriaan Schmitz

Michael Antoine Armand In't Zandt

A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Trench-gate transistors and their manufacture

A vertical insulated gate transistor is manufactured by providing a trench () extending through a source layer () and a channel layer () towards a drain layer (). A spacer etch is used to form gate portions () along the trench side walls, a dielectric material () is filled into the trench between the sidewalls gate portions (), and a gate electrical connection layer () is formed at the top of the trench electrically connecting the gate portions () across the trench.

Vertical insulated gate transistor and manufacturing method

Growing community of inventors

Kessel-lo, Belgium

Gerrit E J Koops