Purdue Research Foundation

Delco Electronics Corporation

Gerold W Neudeck

Rashid Bashir

Chitra K Subramanian

Suresh Venkatesan

Jack L Glenn, Jr

James H Logsdon

Steven E Staller

Percy V Gilbert

David W De Roo

Stephen J Duey

A corner cube array device ( ) is disclosed having a silicon substrate ( ) with a generally cubic crystal lattice. A number of silicon crystal projections ( ) extend from the substrate ( ). The projections ( ) each have three generally planar surfaces, as exemplified by surfaces ( ) of projection ( ), to provide a cube corner shape. Projections ( ) are spaced apart from each other in accordance with a predetermined spatial pattern to define a cube corner array ( ) suitable for optical device applications and the mass production of articles having a substantially similar corner cube array shape.

Corner cube arrays and manufacture thereof

A method of forming a semiconductor-on-insulator (SOI) electronic device includes the steps of etching a semiconductor substrate to form a plurality of adjacent trenches therein and then forming electrically insulating layers on bottoms of the trenches. Epitaxial lateral overgrowth (ELO) is then performed to grow respective monocrystalline semiconducting regions in the trenches. These semiconducting regions are preferably grown from a sidewall of each trench onto a respective insulating layer and fill each trench. Monocrystalline active regions of the electronic device are then formed in the semiconducting regions and also in the substrate, adjacent the trench sidewalls. For example, a monocrystalline trench isolated extrinsic base region of a bipolar junction transistor (BJT) can be formed in a semiconducting region in a respective trench, and a corresponding intrinsic base region and an intrinsic collector region can be formed in the substrate, adjacent the semiconducting region. Alternatively, trench isolated source and drain regions of a field effect transistor (FET) can be formed in one or more adjacent semiconducting regions and the corresponding channel region of the FET can be formed therebetween.

Method of forming semiconductor-on-insulator electronic devices by

A semiconductor-on-insulator (SOI) electronic device includes a monocrystalline semiconductor substrate and at least one trench therein. A trench insulating layer is provided on a bottom the trench for electrical isolation and a monocrystalline semiconducting region is also included in the trench, on the trench insulating layer. The semiconducting region preferably includes epitaxially overgrown silicon (EOS) which is grown from an exposed sidewall of the trench. An active region of the electronic device is also included in the semiconductor layer. Second, third, and additional active regions of the electronic device, if any, may also be included in the semiconducting region or in additional semiconducting regions which are provided in additional trenches. The semiconductor substrate may also include one or more active regions of the electronic device.

Semiconductor-on-insulator electronic devices having trench isolated

A self-aligned process for fabricating high performance bipolar transistors for integrated circuits includes the formation of a collector contact and intrinsic collector region within an opening at the face of a semiconductor substrate. In particular, layers of oxide and polysilicon are formed on the surface of a substrate. An opening is then formed in both layers followed by the implantation of a buried collector region into the substrate at the exposed substrate face through the opening. Polysilicon contacts to the buried layer are then formed on the sidewalls of the opening. These contacts join with the polysilicon layer to form a collector contact. An oxide is then grown on the collector contact. A monocrystalline intrinsic collector is then formed from the exposed substrate face adjacent said collector contact. In this manner, the buried collector, collector contact and intrinsic collector are all formed in a self-aligned manner. Emitter and base regions may then be formed in the intrinsic collector, using techniques to form a completely self-aligned device.

Method for fabricating a triple self-aligned bipolar junction transistor

A quasi-dielectrically isolated (QDI) bipolar structure using epitaxial lateral overgrowth (ELO) uses a combination of dielectric isolation (DI) and junction isolation (JI), providing better isolation properties than JI, while providing better heat dissipation than DI. ELO silicon is grown out of a deep basin with oxide sidewalls for lateral dielectric isolation. The ELO silicon is grown at a low temperature and pressure in an RF heated pancake-type reactor. Fabricated transistors have gains, ideality factors, and leakage currents comparable to bulk devices. A main application for QDI is in power integrated circuits (PICs) where isolation of high power devices and low power logic is necessary.

Method of forming single crystalline electrical isolated wells

Triple self-aligned bipolar junction transistor

A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.

Dual-gated semiconductor-on-insulator field effect transistor

A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer. The first doped region extends toward the first surface between the sixth and seventh regions and separated therefrom by an electrically insulative layer of variable thickness suitable for voltage blocking. An eighth doped region in the first doped region between the sixth and seventh regions abuts the first surface and forms the drain of a MOSFET or the anode of an IGBT. In fabricating the device, reactive ion etching is used to from a trench in which the sixth and seventh regions are formed. The trench is filled by epitaxially grown semiconductor material in which the eighth doped region is formed. The fourth and fifth doped regions form the source of a MOSFET or a cathode of an IGBT. All ohmic contacts to the device can be made on the first surface.

Integrable MOS and IGBT devices having trench gate structure

Methods for fabricating a dual-gated semiconductor-on-insulator field

An integrated circuit vertical bipolar transistor includes monocrystalline emitter, base and collector contacts for electrically contacting the transistor's emitter, base and collector regions, respectively. The collector, base contact and emitter contact are preferably insulated from one another by oxide regions which are formed from the monocrystalline collector and monocrystalline base contacts. Since all of the contacts are formed of monocrystalline material and the oxide isolation is formed from monocrystalline material, high performance devices are formed. The process of forming the transistor self aligns the base to the collector and the emitter to the base. The monocrystalline base contact is also self aligned to the base and the monocrystalline emitter contact is self aligned to the emitter. The process preferably uses epitaxial lateral overgrowth and selective epitaxial growth from a mesa region to form the monocrystalline contacts. A shallow phosphorus implant into the base contact is used to preferentially grow the oxide between the base contact and emitter contact.

Self-aligned integrated circuit bipolar transistor having

A method is disclosed for forming thin, suspended membranes of epitaxial silicon material. Silicon oxide strips having a predetermined thickness are first formed on a silicon substrate. The gap, or spacing, between adjaceant beams is preferably less than or equal to about 1.4 times the thickness of the silicon oxide strip. The underlying silicon substrate is exposed within these gaps in the silicon oxide layer, thereby the gaps provide a seed hole for subsequent epitaxial growth from the silicon substrate. Epitaxial silicon is grown through the seed holes and then allowed to grow laterally over the silicon oxide strips to form a continuous layer of epitaxial silicon over the silicon oxide strips. The backside of the silicon substrate, or surface opposite the surface having the silicon oxide strips, is then masked to delineate the desired diaphragm and microbridge pattern. The silicon is etched conventionally from the backside. Etching is substantially terminated automatically by the presence of the silicon oxide strips. The thin, single crystal silicon membranes are suitable for use as diaphragms and microbridges in a microaccelerometers or pressure sensor.

Method for forming thin silicon membrane or beam

Silicon epitaxial lateral overgrowth (ELO) techniques are employed to fabricate bipolar transistors. ELO bipolar devices have may advantages in reducing parasitic values. Because the heavily doped buried layer (or sub-collector) is eliminated in ELO structures, C.sub.cs is greatly reduced. The concentric collector contact and its closeness to the active collector region reduce r.sub.c in the device. The parasitic collector-to-base capacitance, C.sub.cb, is also reduced due to oxide-isolation. The ELO device is fabricated using standard silicon-processing equipment. ELO can be accomplished on &lt;100&gt; or &lt;111&gt; silicon substrates.

Growing community of inventors

West Lafayette, IN, United States of America

Gerold W Neudeck