Siemens Aktiengesellschaft

Nokia Siemens Networks Gmbh & Co Kg

Gero H Schollmeier

Heinrich Sailer

Christian Winkler

Helmut Koeth

Gunter Boese

Ernst Neudorfer

The invention relates to a method which is used to adapt link weights or, link costs, for optimized traffic distribution within a communication network. According to said method, a loop is circulated until an interruption criterion is met. The individual iterations comprise the following steps: Routing of traffic within the communication network is calculated based on link cost paths. Parameter values used for opt imization e.g. the link-related volume of traffic, are determined for the individual links by means of the calculated path, and an expected volume of traffic and the link are determined for the parameter having the highest value. When the highest determined value is equal to or less than the valve of the previous step (interruption criterion), the link costs are increased for the determined link. Said method enables link costs and paths for optimized traffic distribution to be determined in an economical manner.

Method for adapting link weights in relation to optimized traffic distribution

A method for shortest path routing, optimized for network utilization is provided. The shortest or optimal paths for routing within the network are calculated from initial values for the link costs. The paths comprise possible path alternatives. The number of originally calculated paths is reduced to the set of unique paths (no path alternative), by changing the link costs as a measure of the loading of the individual links, which leads to an optimized loading of the links, in other words an optimized network utilization. The method provides a simple determination of paths for a single shortest path routing, optimized for network utilization.

Shortest-path routing optimized for network utilization

For the compensation of echo signals occuring in the course of the duplex transmission of digital signals by the dual channel system in signal transmission equipment provided with an echo compensator, the equipment is designed so that the clock pulses emitted by a timing generator for the transmission of the digital signals can be shifted in phase by predetermined phase grid steps. When a change in the phase position of the clock pulses takes place within one phase grid step, correction signals are generated, with the phase position that has been accurately set in each case being maintained. These correction signals are subtracted, together with the compensation signals emitted by the echo compensator for the compensation of the echo signals, from the digital signals received together with the echo signals.

Method and circuit arrangement for the compensation of echo signals

A circuit arrangement is disclosed for the summation of products formed from analog signals and digital coefficients. A multiplying digital-analog converter is provided having a reference input for receiving analog signals at successive points in time. A data input of the digital-analog converter receives digital coefficients assigned to the respective analog signals. A summation stage connected to output signals of the digital-analog converter integrates over a predetermined time period the output signals of the digital-analog converter representative of products of the analog signals and digital coefficients.

Circuit arrangement for the summation of products formed by analog

An adaptive or self-adjusting corrector is provided for the correction or equalization of data signals formed with the primary value and a plurality of prior and subsequent oscillations. A plurality of delay members are provided for delaying the data signals. Members for multiplying the data signals by alterable coefficients are provided at outputs of each of the delay members. At least one adder connects with the coefficient members for summing up the multiplied data signals. Either a first coefficient member corresponding to the primary value of the data signal or a second coefficient member corresponding to a first subsequent oscillation of the data signal establish constant coefficients. Alternatively both the first and second coefficients may be made constant. Preferably the constant value is zero.

Adaptive corrector

The invention relates to a novel switching circuit for regulating the repetition rate of clock pulses generated by a clock pulse generator. This repetition rate regulation of the clock pulses thereby controls the sampling instants at which a data signal is sampled. The best possible sampling interest is found by sampling at a first zero crossing of a distorted data pulse after its maximum value. The circuit of the invention generates a first signal which corresponds to the sign of the difference between the actual and the desired values of the data signal at the sampling instants; the circuit also generates a second signal which corresponds to the sign of the desired value of the data signal. A delay element delays the second signal by a period of the clock pulse. A multiplier circuit multiplies the first signal by the delayed second signal and produces an output control signal which regulates the repetition rate of the clock pulse generator.

Switching circuit for regulating the repetition rate of clock pulses

The invention relates to a novel filtering circuit whereby a phase detected output control signal is filtered and utilized to provide greater stability in a phase-locked loop. The filtering circuit is placed in the connecting path between a phase detector and an oscillator; the oscillator supplies output signals, having a repetition rate which depends on the instantaneous values of the filtered control signal. The filtering circuit comprises an adder which adds the phase detected control signal to a signal corresponding to the preceding filtered control signal multiplied by a constant factor which is less than unity (&lt;1).

Filtering circuit for a phase-locked loop

A circuit arrangement is described wherein the pulse repetition frequency of a signal is digitally controlled in dependence on the pulse repetition frequency of a controlling signal. A presettable digital counter functioning as a frequency divider operates between preset initial and end counts and is reset to the initial value each time the end value is reached; the initial and end values are set responsive to binary signals applied to control inputs of the counter. A bistable trigger stage assumes either an idle or an operative state in dependence on the value of a control signal derived from the controlling pulse repetition frequency and a timing signal. The trigger stage output is used to control either the setting of the afore-mentioned initial value or the end value to produce either too high or too low values for the pulse repetition frequency of the controlled signal.

Circuit arrangement for controlling the pulse repetition frequency of a

An equalizer for partial response signals is described which is constituted by a shift register and an analog adder, from the output of which a corrected signal is produced. Two of the switching stages forming the shift register have their outputs connected to inputs of an additional analog adder, and one of these shift register stage outputs is connected to the analog adder over an adjustable amplifier. The output of the additional analog adder is connected to a correlator, the value of the output signal of which controls the gain of the adjustable amplifier.

Equalizer for partial response signals

Apparatus for controlling the phase of a clock signal in a data transmission system is described. In the latter system the data signal is pulse amplitude modulated, routed to a receiver-demodulator over a transmission path, the data signal retrieved by means of a sampling circuit and coupled to a data sink. A difference signal is produced from the demodulated and the data signals; the amplitudes of the difference signal characterize the amplitude differences between the demodulated and the data signals at predetermined sampling instants. Using the demodulated signal a slope signal, which is indicative of the slope of the demodulated signal at the sampling instants is produced. The difference and slope signals are multiplied producing a product signal having amplitudes equal to the product of the latter two signals. The product signal forms a control signal for altering the phase of the clock signal by adding to or suppressing pulses emitted from a frequency divider.

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Gauting, Germany

Gero H Schollmeier