Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

St-ericsson Sa

Sgs Microelettronica Spa

Sgs-thomson Microelectronics S.p.a.

Optis Circuit Technology, LLC

Stmicroelectronics International N.v.

Thomson Microelectronics, S.r.l.

Germano Nicollini

Pierangelo Confalonieri

Sergio Pernici

Daniel Senderowicz

Andrea Barbieri

Marco Zamprogno

Stefano Ramorini

Angelo Nagari

Carlo Pinna

Roberto Modaffari

Alberto Minuti

Riccardo Martignone

Alessandro Gasparini

Alberto Cattani

Federico Guanziroli

Marco Garbarino

Francesca Girardi

Stefano Polesel

Rinaldo Castello

Paolo Pesenti

Carlo Crippa

Edoardo Marino

Federica Barbieri

Giuseppe Palmisano

Guido Torelli

Sebastiano Conti

Alessandro Bertolini

Silvia Adorno

Alessandro Mecchia

Marco Orazio Cavallaro

Alberto Danioni

Luigino D'Alessio

Pierangelo Confaloneri

Fabio Stevenazzi

Massimo Orio

An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Amplifier circuit, corresponding device and method

A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.

Multi-stage amplifier circuits and methods

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Compensation circuit for delta-sigma modulators, corresponding device and method

A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.

Low power voltage reference circuits

A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.

Bandgap reference circuit, corresponding device and method

A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.

Interface circuit and corresponding method

A current mirror includes first and second transistors having current paths coupled to an input current line. The current paths for the first and second transistors are referenced to ground via respective first and second resistors having resistance values twice a first resistance value. The first transistor is diode connected. A third transistor has a current path coupled to an output current line and referenced to ground via a third resistor having a second resistance value equal to the first resistance value divided by a mirror factor. Control terminals of the first and third transistors are coupled together, and further coupled to a control terminal of the second transistor through a coupling resistor. A first capacitor is coupled between ground and the control terminal of the second transistor unit. A second capacitor is coupled between ground and the current path through the third transistor.

Frequency compensation circuit and corresponding device

A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.

Comparator circuit, corresponding device and method

A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

Sensing circuit, corresponding amplifier, apparatus and method

A first current proportional to absolute temperature flows in a first current line through a first p-n junction and a second p-n junction arranged in series. A cascaded arrangement of p-n junctions is coupled to the second p-n junction and includes a further p-n junction with a current flowing therethrough that has a third order proportionality on absolute temperature. A differential circuit has a first input coupled to the further p-n junction and a second input coupled to a current mirror from the first p-n junction, with the differential circuit configured to generate a bandgap voltage with a low temperature drift from a sum of first voltage (that is PTAT) derived from the first current and a second voltage (that is PTAT) derived from the third current.

In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively.

Digital-to-analog converter circuit, corresponding device and method

A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.

Large input swing circuit, corresponding device and method

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Piacenza, Italy

Germano Nicollini