Hayes Microcomputer Products, Inc.

German E Correa

Randy D Nash

Taruna Tjahjadi

Matthew F Easley

Cynthia A Panella

George R Thomas

John N Martin

David F Strawn

Martin H Sauser, Jr

Steven R Sweitzer

Cynthia J Correa

Charles H McCorvey, Jr

Michael L Rubinstein

A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing jitter around the optimal sampling point.

High speed half duplex modem with fast turnaround protocol

An improved V.22 bis 2400 bits per second (bps) handshake sequence detector. An incoming phase keyed (PSK) handshake sequence is autocorrelated using a frequency shift keyed (FSK) receiver (101). The autocorrelated signal is then filtered by a low pass filter (106). The autocorrelated, low pass filtered signal is then alternately fed, at a 1200 Hz rate, to two detectors (114,116). Each of the detectors (114,116) looks for one half of the handshake sequence. The output of each detector (114,116) is provided to an OR-gate (122). The 2400 bps handshake sequence is declared to be detected when either one or both of the detectors (114,116) detects its corresponding portion of the sequence.

Autocorrelating 2400 bps handshake sequence detector

An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.

Method and apparatus for generating a data sampling clock locked to a

A modem and an improved phase-locked loop used in the modem. A presettable counter (251) generates the desired signal (TXCLKOUT). The reference input clock signal (TXCLKIN) and the generated clock signal (TXCLKOUT) are compared by an exclusive-OR gate (254). The output of the gate (254) is sampled by two flip-flops (256,266) before and after a rising edge of the TXCLKOUT signal. If the TXCLKIN and TXCLKOUT signals differ by more than a desired phase window a logic circuit (264) adjusts the preset inputs of the counter (251) so that the TXCLKIN and TXCLKOUT signals are in phase within the desired phase window.

Phase-locked loop for a modem

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Alpharetta, GA, United States of America

German E Correa