Raytheon Company

Kenet Incorporated

Intersil Americas Inc.

Raytheon Bbn Technologies Corp.

Gerhard Sollner

Matthew A Morton

Michael P Anthony

Lawrence J Kushner

Jason C Soric

Thomas E Kazior

Eduardo M Chumbes

Moe Soltani

Shahed Reza

Thomas M Hartnett

Edward Kohler

Jason D Adams

Jack W Holloway

Ken Dinndorf

William D Washkurak

Wesley Grant

Poornima Varadarajan

Evelina Aleksandro Polyzoeva

A technology is described for a Photonic Integrated Circuit (PIC) radio frequency (RF) oscillator. The PIC RF oscillator can comprise an optical gain media coupled to a first mirror and configured to be coupled to the PIC. The PIC can comprise a first optical cavity located within the PIC, a tunable mirror to form a first optical path between the first mirror in the gain media and the first tunable mirror, and a frequency tunable intra-cavity dual tone resonator positioned within the first optical cavity to constrain the first optical cavity having a common optical path to produce tow primary laser tones with a tunable frequency spacing. A photo detector is optically coupled to the PIC and configured to mix the two primary laser tones to form an RF output signal with a frequency selected by the tunable frequency spacing of the two primary tones.

Photonic integrated circuit (PIC) radio frequency oscillator

Methods and apparatus for a frequency selective limiter (FSL) having a magnetic material substrate that tapers in thickness and supports a transmission line that has segments and bends. The segments, which differ in width and are substantially parallel to each other, such that each segment traverses the substrate on a constant thickness of the substrate.

Transversely tapered frequency selective limiter

A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a magnetic material having first and second opposing surfaces. A first conductor is disposed on the first surface of the magnetic material, where a width of the first conductor decreases from a first end of the FSL to a second end of the FSL along a length of the FSL. Two second conductors are disposed on the second surface of the magnetic material, where a width of a gap between the two second conductors decreases from the first end of the FSL to the second end of the FSL along a length of the FSL. The first conductor and two second conductors form a biplanar waveguide transmission line.

Biplanar tapered line frequency selective limiter

A frequency selective limiter (FSL) having an input port and an output port can comprise a plurality of vertically stacked transmission line structures. Each of the transmission line structures can be electrically coupled to a transmission line structure disposed directly above it and with a first one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL input port and a second one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL output port. Each of the plurality of vertically stacked transmission line structures can comprise a magnetic material having first and second opposing surfaces and one or more conductors disposed on at least one of the surfaces of the magnetic material.

Vertically meandered frequency selective limiter

A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a substrate having a magnetic material, a signal (or center) conductor disposed on the substrate and first and second ground plane conductors disposed on the substrate. The signal conductor having a first end with a first width and a second end with a second different width such that the signal conductor is provided having a taper between the first and second ends of the signal conductor. First and second ground plane conductors are spaced apart from first and second edges of signal conductor, respectively, by a distance that changes from the first end of signal conductor to the second end of signal conductor such that signal conductor, and first and second ground plane conductors form a co-planar waveguide transmission line.

Frequency selective limiter

The present disclosure is directed towards a frequency selective limiter having a first magnetic material disposed over a first dielectric material and a strip conductor disposed over the magnetic material. In some embodiments, the frequency selective limiter includes a second magnetic material disposed over the strip conductor and a second dielectric material disposed over the second magnetic material. The first and second dielectric material may have a lower relative permittivity than the first and second magnetic material. In an embodiment, the frequency selective limiter includes a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.

A semiconductor structure having: a Group III-N channel layer, a Group III-N top-barrier polarization-generating layer forming a heterojunction with an upper surface of the channel layer; and a Group III-N back-barrier polarization-generating layer forming a heterojunction with a lower surface of the channel layer. The channel layer has disposed therein a predetermined n-type conductive dopant.

Double heterojunction group III-nitride structures

A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.

Background calibration of offsets in interleaved analog to digital converters

A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.

Doped plug for CCD gaps

A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

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Winchester, MA, United States of America

Gerhard Sollner