Infineon Technologies Ag

Other

Infineon Technologies North America Corp.

International Business Machines Corporation

Siemens Aktiengesellschaft

Qimonda Ag

Qimonda Ag I.in.

Gerhard Kunkel

Shahid Ahmad Butt

Carl John Radens

Hua Shen

Jenny Lian

David Edward Kotecki

Uwe Paul Schroeder

Scott Josef Bukofsky

Alan C Thomas

Satish D Athavale

Oliver Genz

Jurgen Preuninger

Jack Allan Mandelman

Ramachandra Divakaruni

Richard Stephan Wise

Laertis Economikos

Peter Baars

Martin Gutsche

Alois Gutmann

Munir D Naeem

Mihel Seitz

Fen Fen Jamin

Alfred K Wong

Young-Jin Park

Joseph P Kirk

Nirmal Chaudhary

Helmut Wurzer

Lothar Bauch

William Roberts

Bruno Spuler

Christopher Gould

Wolfgang Henke

Hermann Sachse

Armin M Reith

Karl Schumacher

Patrick Lomtscher

Juergen Preuninger

Xiaoming Yin

Nimal Chaudhary

Christian Summerer

One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.

Memory devices including semiconductor pillars

The invention relates to a method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer. An exposure device () is provided, which can emit light in two polarization planes (). Through the choice of the degree of polarization, i.e., the ratio of the intensity in the first polarization plane () to the intensity in the second polarization plane (), it is possible to alter the ratio of width () to length () of the resist structure () formed on the resist layer (). A variation of approximately 30% with respect to dimensionally accurate imaging can thus be achieved in a simple manner.

Method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer

A photolithographic mask having half tone main features and perpendicular half tone assist features. One embodiment provides for the exposure of radiation-sensitive resist layers on semiconductor substrates. The mask has at least one radiation-transmissive substrate and at least one half-tone layer. The half-tone layer is used to provide main features, the main features being formed in such a way that the pattern formed by the main features is transferred into the resist layer when irradiated, and the half-tone layer is also used to provide assist features, the assist features being formed substantially perpendicular to the main features in such a way that the pattern formed by the assist features is not transferred into the resist layer when irradiated.

Photolithographic mask having half tone main features and perpendicular half tone assist features

A first and a second phase-shifting, semitransparent layer are formed on a substrate. The layers are patterned lithographically to form first elevated structure elements on the substrate with a first degree of transmission and second structure elements with a second degree of transmission, where the second degree of transmission is different from the first degree of transmission. Memory products can be produced with high resolution and high dimensional accuracy when the structure elements are transferred to a semiconductor substrate, by virtue of dense structure arrangements being represented by the structure elements with a high degree of transmission of more than 30% and, on the same mask, isolated structure arrangements having a low density being represented by the structure elements with a lower degree of transmission.

Method for producing a phase mask

An inspection system includes an illumination source configured to illuminate a blazed phase grating sample, image collection pathways and an imaging system configured to capture an image of a sample point of the blazed phase grating sample, and a controller configured to adjust the illumination source in response to an analysis of the image of the sample point to determine illumination uniformity of the inspection system.

Optimizing light path uniformity in inspection systems

The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the condition that the product of surface area and transmission of the electrical field strength is the same for all of the portions. Then, frequency doubling occurs due to vanishing zero order diffraction orders and in the case of high-transition attenuated phase-shift masks a large first order diffraction amplitude reveals an even an improved as compared with conventional phase-shift masks. Two-dimensional matrix-like structures particularly on attenuated or halftone phase-shift masks can be arranged to image high-density patterns on a semiconductor wafer. The duty cycles of pattern matrices can be chosen being different from one in two orthogonal directions nevertheless leading to frequency doubling.

Phase-shift mask

Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion thereof. Each buried bit line is formed in a trench in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator and has a conductor in a bottom portion thereof.

Buried bit line-field isolation defined active semiconductor areas

A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of incidence with respect to a surface of the photolithographic mask. The photolithographic mask includes a substantially transparent mask substrate and one or more lines and spaces patterns formed on the mask substrate and having a periodicity P. The mask substrate includes at least one phase shifting region. At least part of the light that is transmitted through the photolithographic mask is collected using one or more projection lenses which project the portion of the transmitted light onto the material substrate. The material substrate is disposed substantially parallel with, but at a distance from, a focal plane of the projection lens system. The phase shifting region of the mask substrate and the distance from the focal plane are selected such that a substantially focused image is projected onto the material substrate that includes the lines and spaces patterned but with a periodicity P/2.

Method of reducing pitch on semiconductor wafer

An apparatus ( ) for patterning the surface of a semiconductor wafer ( ). A stage ( ) is coupled to a motor ( ) that is adapted to move the stage ( ) and a semiconductor wafer ( ) in a horizontal direction at a first speed A. A mask ( ) is disposed above the semiconductor wafer ( ), the mask ( ) being coupled to a motor ( ) that is adapted to move the mask ( ) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens ( ) is used. The mask ( ) and the wafer ( ) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask ( ) pattern onto the wafer ( ) surface.

Apparatus for patterning a semiconductor wafer

In an overlay measurement mark comprising an inner box and an outer box located at a predetermined area on a mask through which patterns are formed on a semiconductor device, the improvement of an overlay mark that extends the overlay measurement range comprising: in-focused marks means printed at an optimal or ideal focal plane level from an illumination source, and de-focused marks means located at a different focus level from the optimal focal plane to provide image placement shift of the de-focused marks larger than that of the in-focused marks means to enable measurement of the shift of de-focused marks that are not attributable to a mechanical alignment error to be determined with greater accuracy.

Enhanced overlay measurement marks for overlay alignment and exposure tool condition control

Methods and reticles for evaluating lenses are disclosed. In one instance, a reticle which permits light to pass therethrough is provided which includes a first surface with a grating profile formed thereon. The grating profile includes a plurality of grouped stepped portions. Each group of the stepped portions includes a first step which prevents light from propagating therethrough, a second step which propagates light therethrough and a third step which propagates light therethrough at an angle 60 degrees out of phase with the light propagated through the second step.

Grating patterns and method for determination of azimuthal and radial aberration

A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the impinging light, such radiated light being radiated with a wavelength different from the wavelength of the impinging light. Also a method and apparatus for detecting an alignment mark on a semiconductor body. The method and apparatus successively scan an alignment illumination comprising the impinging light over the surface of the semiconductor surface and over the alignment mark. The impinging energy is reflected by the surface of the semiconductor when such impinging light is over and is reflected by the surface of the semiconductor. The impinging energy is absorbed by the material and is then radiated by the material when such impinging energy is scanned over such material. The reflected light is selectively filtered while the radiated light is passed to a detector.

Semiconductor structures and manufacturing methods

A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening

A method and apparatus ( ) for patterning the surface of a semiconductor wafer ( ). A stage ( ) is coupled to a motor ( ) that is adapted to move the stage ( ) and a semiconductor wafer ( ) in a horizontal direction at a first speed A. A mask ( ) is disposed above the semiconductor wafer ( ), the mask ( ) being coupled to a motor ( ) that is adapted to move the mask ( ) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens ( ) is used. The mask ( ) and the wafer ( ) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask ( ) pattern onto the wafer ( ) surface.

Apparatus and method for patterning a semiconductor wafer

A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position. The clusters may be in the shape of a hexagon or a diamond.

Multiple exposure process for formation of dense rectangular arrays

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Radebeul, Germany

Gerhard Kunkel