Nxp B.v.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Gerhard Koops

Greja Johanna Adriana Maria Verheijden

Roel Daamen

Jozef Thomas Martinus Van Beek

Johannes Van Wingerden

Wim Van Den Einden

Peter G Steeneken

Erwin Hijzen

Kim Phan Le

Tony Vanhoucke

Anco Heringa

Philippe Meunier-Beillard

Rob Van Dalen

Maarten Jacobus Swanenberg

Johannes Donkers

Henk Boezen

Dusan Golubovic

Reinout Woltjer

Didem Ernur

Alessandro Ferrara

Harold Roosen

Jozef Thomas Beek

Boni Kofi Boksteen

Cas Van Der Avoort

Greja Johanna Adriana Verheijden

Frans Bontekoe

A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.

Method of manufacturing a device with a cavity

A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.

Micro-device with a cavity

Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Field plate assisted resistance reduction in a semiconductor device

A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Piezo-resistive MEMS resonator

A method of manufacturing a MEMS device comprises forming a MEMS device element. A sacrificial layeris provided over the device element and a package cover layeris provided over the sacrificial layer. A spacer layeris formed over the sacrificial layer and is etched to define spacer portions adjacent an outer side wall of the sacrificial layer. These improve the hermetic sealing of the side walls of the cover layer

MEMS devices

The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Interface for communication between voltage domains

A method of manufacturing a structure (), the method comprising forming a cap element () on a substrate (), removing material () of the substrate () below the cap element () to thereby form a gap () between the cap element () and the substrate (), and rearranging material of the cap element () and/or of the substrate () to thereby merge the cap element () and the substrate () to bridge the gap ().

Sealing structure and method of manufacturing the same

Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNH, wherein x&#x3e;1.33 and y&#x3e;0. A method of forming such a device is also disclosed.

Device with microstructure and method of forming such a device

A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.

Microscopic structure packaging method and device with packaged microscopic structure

A micro-device with a cavity, the micro-device including a substrate. A method of forming the micro-device includes the steps of: A) providing the substrate having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant; and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity , i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.

An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Optocoupler circuit

A MEMS resonator, comprising a planar resonator body formed of two different materials with opposite sign temperature coefficient of Young's modulus. A first portion of one material extends across the full thickness of the resonator body. This provides a design which allows reduced temperature drift.

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Aalst, Belgium

Gerhard Koops