International Business Machines Corporation

Gerhard Hellner

Rolf Sautter

Alexander Fritsch

Iris Maria Leefken

Tobias Werner

Michael B Kugel

Silke Penth

Otto M Wagner

Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.

Layout of interconnect lines in integrated circuits

An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal. The amplifier is further configured to generate a second logical value at the first output terminal of the amplifier in response to the sense current being higher than the reference current.

Current-mode sense amplifier and reference current circuitry

An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal. The amplifier is further configured to generate a second logical value at the first output terminal of the amplifier in response to the sense current being higher than the reference current.

The invention relates to a current sense amplifier. The current sense amplifier comprises: a first NAND gate comprising an output terminal being connected to a first output terminal, a second NAND gate comprising an output terminal being connected to a second output terminal, a first cross coupled inverter, and a second cross coupled inverter, the first inverter comprising a first n-FET and the second inverter comprising a second n-FET, a transmission gate comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to a sense control line input terminal, a third n-FET having a source connected to a sense current input terminal and a drain connected to a source of the first n-FET, a fourth n-FET having a source connected to a reference current input terminal and a drain connected to a source of the second n-FET.

Current-mode sense amplifier

The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block ( ), whereby the first and second memory block ( ) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines ( ) and a first set-of match lines ( ) associated to said first memory block ( ), and a second set of compare lines ( ) and a second set of match lines ( ) associated to said second memory block ( ), and pre-charge units ( ) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value. This is achieved by a CAM according to the above features using the pre-charge state of the match lines ( ) as a logically valid state.

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Schoenaich, Germany

Gerhard Hellner