Epcos Ag

Qualcomm Incorporated

Tdk Electronics Ag

Gerhard Fuchs

Sebastian Brunner

Christian Faistauer

Franz Rinner

Christian Block

Christoph Auer

Dieter Somitsch

Stefan Leopold Hatzl

Kurt Wiesbauer

Pavol Dudesek

Klaus-Dieter Aichholzer

Stefan Obermair

Edmund Payr

Guenter Pudmich

Annette Fischer

Franz Tinauer

Stefan Leitinger

Andreas Haas

Florian Rak

Horst Uwe Faulhaber

Yasuharu Miyauchi

Manfred Fischer

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, a buffer dielectric layer coupled to the at least one dielectric layer, and a buffer interconnect located at least in the buffer dielectric layer.

Package comprising a substrate that includes a stress buffer layer

A method for producing a multilayer component () is specified, which involves providing a body having dielectric layers () arranged one above another and first and second electrically conductive layers () arranged therebetween. The first conductive layers () are connected to a first auxiliary electrode () and the second conductive layers () are connected to a second auxiliary electrode (). The body () is introduced into a medium and a voltage is applied between the first and second auxiliary electrodes () for producing a material removal. Furthermore, a multilayer component is specified, which has depressions () formed by an electrochemically controlled material removal.

Method for producing a multi-layer component and multi-layer component

A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Chip with protection function and method for producing same

A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.

Carrier device, arrangement comprising such a carrier device, and method for patterning a layer stack comprising at least one ceramic layer

Growing community of inventors

Steinerkirchen, Austria

Gerhard Fuchs