Hewlett Packard Enterprise Development LP

Vmware, Inc.

Gerd Zellweger

Dejan S Milojicic

Izzat El Hajj

Alexander Merritt

Paolo Faraboschi

Jayneel Gandhi

Amy Tai

Lalith Suresh

Stanko Novakovic

The present disclosure provides an approach for granting access to a resource located on a first server, the granting being done by a second server to a third server. The method results in a decentralized granting of access to a resource, preventing a bottleneck in the first server that could develop if the first server were to grant each access to each of its resources. The access is provided in the form of an encrypted capability, and transmitted through a secure channel. The code on the second server for granting access is located within an encrypted memory region, such that unauthorized processes cannot access the code or the data within the encrypted memory region.

Decentralized sparse capability system with secure enclaves

Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

Server virtual address space

Techniques for efficiently managing the interruption of user-level critical sections are provided. In certain embodiments, a physical CPU of a computer system can execute a critical section of a user-level thread of an application, where program code for the critical section is marked with CPU instruction(s) indicating that the critical section should be executed atomically. The physical CPU can detect, while executing the critical section, an event to be handled by an OS kernel of the computer system and upon detecting the event, revert changes performed within the critical section. The physical CPU can then invoke a trap handler of the OS kernel, and in response the OS kernel can invoke a user-level handler of the application with information including (1) the identity of the user-level thread, (2) an indication of the event, (3) the physical CPU state upon detecting the event, and (4) an indication that the user-level thread was interrupted while in the critical section.

Efficiently managing the interruption of user-level critical sections

Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).

Persistent virtual address spaces

According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

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Palo Alto, CA, United States of America

Gerd Zellweger