Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Gerd Rombach

Ingolf Frank

Hermann Seibold

Sotirios Tambouris

Georg Becke

Soritios Tambouris

Miki Moyal

In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

Continuous coarse-tuned phase locked loop

An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P-and N-N; and a means for weighting (sizing) of transistor (P& P) relative to Pand (N& N) relative to Ndefines the optimal operation mode.

High speed, rail-to-rail CMOS differential input stage

The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Data pipeline with large tuning range of clock signals

A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Register with process, supply voltage and temperature variation independent propagation delay path

A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Phase-locked loop (PLL) circuit and method

A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference path includes a third data register. A learn cycle control signal is applied to a multiplexer for selecting between the data path and the reference data path and is also applied in parallel to control circuitry of a phase aligner. The learn cycle control signal is for adjusting the phase of a clock signal at a second clock output of a phase locked loop so as to optimize setup and/or hold timing at the data input of the second data register.

Digital data buffer with phase aligner

A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.

Phase-locked loop circuit

A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where 

PLL circuit having reduced capacitor size

A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator ( ), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator ( ), the oscillating frequency of which can be cycled in the predefined range. The second oscillator ( ) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Clock generator circuit with a PLL having an output frequency cycled in a range to reduce unwanted radiation

An integrated fast bus driver circuit with reduced standby power consumption for BiCMOS processes where the power consumption of the drive circuit corresponds to the output sink current. A feedback circuit is connected to detect voltage variations at the output terminal, and vary the base current of the output bipolar transistor to oppose the voltage variations.

Fast bus driver with reduced standby power consumption

The invention relates to a 'power on demand' control circuit and the application thereof in a BiCMOS bus driver. The basic object resides in the creation of such a circuit with a low power need and a simple structure. This aim is to be solved by the provision of a control loop comprising a diode series circuit arrangement (D1, D2) and a bipolar transistor (Q2) between the collector and the base of the output transistor (Q1), which is of such a size that in the stable L state the base current of the outlet transistor (Q1) is so selected that the L state is maintained.

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Freising, Germany

Gerd Rombach