U.S. Philips Corporation

Gerd Onken

Jorg Wolber

Dieter J Kunze

Matthias Peters

Wilhelm Graffenberger

Ulrich Mohlmann

A digital phase-locked loop (PLL) which responds to a square-wave input signal of on expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals or different frequencies and precedes a main divider operating with a divisor D and which produces the output signal of the phase-locked loop. The change-over switch is activated as a function of the output signal and the input signal. In order to provide symmetrical locking in of the phase-locked loop and a small capture-and-hold range, the change-over switch is switched between a first square-wave signal of the frequency f.sub.1, a second square-wave signal of the second frequency f.sub.2 and a third square-wave signal of the frequency f.sub.3, in which:

Digital phase-locked loop

Circuitry for processing, in a television signal, a first, low-frequency synchronizing signal on which a second, high-frequency synchronizing signal is superposed, for supplying standardized television signal capable of being processed by a customary television signal processing arrangement or display device, respectively by inhibiting a shift between the picture content of the signal representing the television signal and the synchronizing signal. The circuitry includes a first signal processing branch (1) having a low-pass filter (11) for separating low-frequency components and consequently the first synchronizing signal (Sy1) from the television signal, a synchronizing pulse detector (12) for detecting signal variations exceeding a cut-off level (SP) in the low-frequency components, and also a pulse generating stage (13) for producing a pulse when such a signal variation corresponding to a synchronizing pulse of the first synchronizing signal (Sy1) is detected, the pulse being of a duration shorter than the shortest second synchronizing signal (Sy2), a second signal processing branch (2) having a halfwave detector (21) for separating signal peaks exceeding maxima (MaSy1) of the first synchronizing signal (Sy1) from the television signal and for charging a signal store (23) in a first direction during a time interval corresponding to the period of the second synchronizing signal (Sy2), in which the signal peaks occur, and also a third signal processing branch (3) producing a constant reference level during a time interval wherein either a pulse is supplied in the first signal processing stage (1) or the signal store (23) is charged in the first direction, instead of the television signal produced in the remaining time.

Circuitry for processing a synchronizing signal

A circuit arrangement for transferring a d.c. voltage via a smoothing network including a capacitor which can be switched to prevent a surge in the transferred signal from occurring. The voltage from the output terminal is applied to the capacitor in the changed-over state via an amplifier having a high input impedance and a gain factor of substantially 1.

Switchable smoothing network

A push-pull B-stage in IC is arranged with an additional transistor in such a manner that one transistor in the IC and the additional transistor together constitute a new push-pull amplifier while the transistor in the IC is loaded to a higher extent and the other final stage transistor in the IC only serves as a driver for the additional transistor.

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Hamburg, Germany

Gerd Onken