Telefonaktiebolaget Lm Ericsson (publ)

Siemens Aktiengesellschaft

Gerd Mörsberger

Ralf Kukla

Georg Spörlein

Stefan Schütz

Lars Lauer

Josef Deuringer

Richard Eichhorn

Edmund Goetz

Paul Ponnath

Roland Rabe

Gerhard Goedert

A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.

Housing comprising a liquid-tight electric bushing

This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.

Apparatus and method for flexible data rate matching

A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

Interleaving for mobile communications

This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

Speed and memory optimized interleaving

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Bubenreuth, Germany

Gerd Mörsberger