Other

Gerd Fehlauer

Jack Allan Mandelman

Helmut Horst Tews

Rama Divakaruni

Stephan Kudelka

Uwe Schroeder

A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

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Unterhaching, Germany

Gerd Fehlauer