Infineon Technologies Ag

Gerd Dirscherl

Berndt Gammel

Bernd Meyer

Thomas Nirschl

Steffen Sonnekalb

Philip Schlazer

Rainer Goettfert

Christian Peters

Robin Boch

Jan Otterstedt

Stefan Rueping

Albrecht Mayer

Thomas Kuenemund

Gunther Fenzl

Michael Smola

Holger Sedlak

Ronald Kakoschke

Wieland Fischer

Oliver Kniffler

Marcus Janke

Norbert Janssen

Jean-Pierre Seifert

Arno Rabenstein

Franz Klug

Joel Hatsch

Tobias Schlager

Markus Gail

Witold Gora

Roth Manfred

Nikolai Sefzik

Andreas Geiler

Benedikt Driessen

Stefan Erdmenger

Wolfgang G&auml;rtner

Marcel Schaible

J&uuml;rgen Nolles

Bernhard Sommer

Min Wei Ang

Udo Kriebel

It is proposed to divide data read from a memory into groups and to perform a syndrome calculation iteratively based on each of the individual groups. The syndromes may be calculated by means of random access to the individual groups.

Processing of data read from a memory

A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.

Address-coded access towards memory

A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Memory circuit and method of operating a memory circuit

A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Data encryption and verification between master and slave

Memory circuit including overlay memory cells and method of operating thereof

A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

Memory circuit including at least one marking cell and method of operating said memory circuit

In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

Method for accessing a memory and memory access circuit

A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

Method for determining an intergrity of an execution of a code fragment and a method for providing an abstracted representation of a program code

A method for generating a data frame is disclosed which contains a user data block with the message and a code block. To generate the code block, a first data record is initially coded by means of a first coding algorithm in order to calculate a first code word. Subsequently, the message is transformed. By using the first code words thus generated and the transformed message, a second code word is subsequently calculated by using a second coding algorithm. The data frame comprises the second code word but not the first code word.

Data frame for protected data transmissions

An apparatus and corresponding method for preventing cloning of code. The apparatus includes a memory, an authentication module, and a device. The memory is configured to store the code, which includes unencrypted code and a fragment of encrypted code. The authentication module is configured to receive and decrypt the fragment of encrypted code from the memory into a fragment of decrypted code, and to store the fragment of decrypted code in an authentication module buffer. The device configured to execute the unencrypted code from the memory and to execute the fragment of decrypted code from the authentication module buffer, wherein the fragment of encrypted code is personalized to the device.

Apparatus and method for preventing cloning of code

A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Data processing arrangement and method for data processing

An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.

System on chip with embedded security module

A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF Aand performing a preliminary correction of the potentially erroneous PUF Aby means of a stored correction vector Delta, to obtain a preliminarily corrected PUF B. The PUF A is reconstructed from the preliminarily corrected PUF Bby means of an error correction algorithm. A corresponding apparatus is also provided.

Apparatus and method for reconstructing a bit sequence with preliminary correction

An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Integrated circuit and method for manufacturing the same

The invention relates to methods and systems for securely transferring embedded code or data to a customer, in particular to methods and systems for securely transferring embedded code, data files or program files designed for a device to a customer in order to prevent the embedded code, data files or program files from being used on unauthorized devices.

Growing community of inventors

Munich, Germany

Gerd Dirscherl