Taiwan Semiconductor Manufacturing Comp. Ltd.

Nxp B.v.

Gerben Doornbos

Marcus Johannes Henricus Van Dal

Georgios Vellianitis

Mark Van Dal

Matthias Passlack

Blandine Duriez

Mauricio Manfrini

Martin Christopher Holland

Timothy Vasen

Krishna Kumar Bhuwalka

Chung-Te Lin

Peter Ramvall

Richard Kenneth Oxland

Carlos H Diaz

Robert James Pascoe Lander

Thomas Merelle

Tsung-Lin Lee

Feng Yuan

Chien-Hsun Wang

Radu Surdeanu

Robert James Lander

Georgios Vallianitis

Oreste Madia

Marcus Van Dal

Chun-Hsiung Lin

Peter Dirksen

Shih-Wei Wang

Jan Sonsky

Jan Willem Slotboom

Aryan Afzalian

David Van Steenwinckel

Godefridus A M Hurkx

Prabhat Agarwal

Gilberto Curatola

Pierre Goarin

Casper Juffermans

Yee-Chaung See

Anja Vanleenhove

Krishna Bhuwalka

The present disclosure relates to an integrated chip including a channel structure on a first substrate. A gate electrode overlies the channel structure. A first source/drain structure abuts the channel structure and is offset from the gate electrode. A conductive structure is disposed on the first substrate and underlies the first source/drain structure. A first contact extends from the first source/drain structure to the conductive structure.

Integrated chip having a buried power rail

Ferroelectric field effect transistors are in a three-dimensional structure that includes vertical columns. Source/drain electrodes are provided by horizontal conductive layers that are interleaved with dielectric layers. Channels for the FeFETs in each vertical column are provided by a continuous semiconductor layer, e.g., a vertical strip of semiconductor. Another vertical strip may provide the ferroelectric layers for the FeFETs in the vertical column. The gate electrodes are provided by a control gate structure that connects the gate electrodes in parallel. The source/drain electrodes of multiple vertical columns may be connected in parallel. The source/drain electrodes of multiple tiers may also be connected in parallel. This structure provides high area density, adds an extra degree of freedom in circuit design, and lends itself to the use of oxide semiconductor channels.

Vertically stacked FeFETs with common channel

A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

Semiconductor device including back side power supply circuit

A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.

Semiconductor device including first and second transistor channels

A semiconductor structure includes a substrate; a resistance variable layer disposed over the substrate; a gate structure disposed over the resistance variable layer; a dielectric layer disposed over the resistance variable layer and surrounding the gate structure; a first contact plug disposed over the resistance variable layer and extending through the dielectric layer; and a second contact plug disposed over the resistance variable layer and opposite to the first contact plug and extending through the dielectric layer, wherein the resistance variable layer is semiconductive and ferroelectric. A method of manufacturing a semiconductor structure is also disclosed.

Semiconductor structure and manufacturing method thereof

A ferroelectric device and a wave computing device are provided. The ferroelectric device includes a first electrode, a second electrode, a ferroelectric layer and a wave guide. The ferroelectric layer is disposed between the first and second electrodes, and configured to transduce an electrical wave signal to a varying mechanical stress by piezoelectricity, or vice versa. A first polarization state or a second polarization state opposite to the first polarization state is programmed in the ferroelectric layer. The wave guide is in contact with the ferroelectric layer, and configured to transmit a wave signal resulted from or resulting the varying mechanical stress. The wave signal is in phase with the electrical wave signal when the ferroelectric layer is programmed with the first polarization state. The wave signal is out of phase with the electrical wave signal when the ferroelectric layer is programmed with the second polarization state.

Ferroelectric device and wave computing device

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Access transistor including a metal oxide barrier layer and methods for forming the same

A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layerhas a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Protrusion field-effect transistor and methods of making the same

A field effect transistor may include an active layer containing an oxide compound material of at least two atomic elements including a first element of tin and a second element selected from Ge, Si, P, S, F, Ti, Cs, and Na and located over a substrate. The field effect transistor may further include a gate dielectric located on the active layer, a gate electrode located on the gate dielectric, and a source contact structure and a drain contact structure contacting a respective portion of the active layer. The oxide compound material may include at least germanium and tin. The oxide compound semiconductor material may be used as a p-type semiconductor material in BEOL structures.

Germanium tin oxide-containing semiconductor device and methods for forming the same

A semiconductor device is provided. The semiconductor device includes a logic structure overlying a semiconductor substrate of the semiconductor device. The logic structure includes a plurality of logic cells. The semiconductor device includes one or more interconnection layers, overlying the logic structure, in a Back End of Line (BEOL) structure of the semiconductor device. The semiconductor device includes a non-volatile memory array, including a plurality of memory cells, overlying the logic structure and the one or more interconnection layers, wherein the non-volatile memory array at least one of overlies or is within the BEOL structure.

Memory array structure

A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Semiconductor structure and method of forming the same

In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.

Semiconductor device having fin structures with unequal channel heights and manufacturing method thereof

A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.

Method for forming semiconductor device with transistors on opposite sides of a dielectric layer

A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.

Complementary MOS FETS vertically arranged and including multiple dielectric layers surrounding the MOS FETS

A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.

Growing community of inventors

Leuven, Belgium

Gerben Doornbos