U.S. Philips Corporation

Gerardus C Gielis

Rudy J Van De Plassche

Theodoor A Claasen

Alphons A Bruekers

Johan M Schmidt

Steven J Van Lerberghe

Antonius J Bogers

Harry B Schoonheijm

Antoon M Van Kessel

Rudy J Van Der Plassche

A signal processor has an X-Y rotation circuit and a phase angle control circuit, in the phase angle control circuit, an input phase being approximated by a series of consecutive, in magnitude, decreasing phase angles for forming an output vector by rotation of an input vector over the approximation of the input phase. In the phase angle control circuit, an accuracy of the representation of a phase angle out of the series of phase angles, is dependent on the magnitude of the phase angle, thereby reducing the number of computations in the phase angle control circuit.

Signal processor with reduced complexity, and receiver comprising such a

In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).

Receiver with quadrature decimation stage, method of processing digital

Receiver having an A/D converter for digitally sampling an analog signal modulated on a carrier frequency at a first sampling frequency, consecutively coupled to a digital quadrature mixer stage for a carrier frequency shift of the digitized modulated signal from the A/D converter, a digital filter device for selecting the phase quadrature signals of the quadrature mixer stage and for decimating the sampling frequency from the first sampling frequency to a second sampling frequency, and a digital demodulation device. To obtain a receiver which can be easily realized in an integrated form and for which less crystal surface is required than for the digital integrable receivers hitherto known, and which is particularly suitable for receiving RF radio or TV broadcast signals, the digital quadrature mixer stage includes comprises a first coordinate rotation digital computer (Cordic) in the rotation mode, having at least a first signal input which is coupled to an output of the A/D converter and a phase signal input to which a periodical digital sawtooth-shaped phase signal is applied from a digital sawtooth generator for a periodical 2.pi. phase rotation of at least the signal applied to the computer via the first signal input at a repetition frequency which is equal to the magnitude of the carrier frequency shift.

Receiver

A digital lattice filter, comprising a plurality of identical stages each having a pair of inputs for receiving input signals and a pair of outputs for supplying output signals, these stages being connected in a cascade arrangement, each stage consisting in two mutually linked branches and no less than one of these branches comprising delay means, and in that always an even number of successive cascaded filter stages forms a group, in which both branches of each group of filter stages comprise a delay elements such that the time delay in the first branch is equal to the time delay in the second branch.

Digital lattice filter

FM-receiver for receiving an FM-signal with transmission identification. An aerial input is connected to a tuning unit (1) to which there are connected, in succession, an IF-unit (2), an FM-detection circuit (3), a pilot regeneration circuit (10) for regenerating a pilot, a demodulation arrangement (12) for demodulating the code signal which contains transmission identification information, and a clock regeneration circuit (18) which is connected to both the pilot regeneration circuit (10) and the demodulation arrangement (12). The clock regeneration circuit comprises a resettable phase search circuit (18') for producing a clock signal whose frequency is derived from the regenerated pilot and whose phase is derived from the demodulated code signal, a clock-controlled decoding circuit (13) for decoding the code signal and a clock-controlled signal processing unit (17). For the purpose of stabilizing the processing, for example, for the reproduction of the transmission identification information, more specifically with mobile reception, use is made, in the event of disturbances of the code signal, of correctly decoded bits which were stored during undisturbed reception in a memory circuit ( 15). Only in the event of extreme interferences the phase search circuit (18') of the clock regeneration circuit (18) and also the other clock-controlled circuits (13-17) are reset to correct a possible phase slip of the clock signal.

FM-receiver for receiving FM-signals with transmission identification

An FM-receiver with transmitter characterization, having a tuning unit, an IF-amplifier, a demodulation circuit for demodulating a discrete transmitter characterization signal, a clock regeneration circuit, a decoding device for decoding the discrete transmitter characterization signal and a signal processing unit. The clock regeneration circuit regenerates a clock signal the period of which is obtained by dividing the frequency of the stereo pilot signal. Synchronization of the clock signal phase with the phase of the clock signal used in the transmitter is carried out by detecting, using of a periodic window signal, the average phase of the code edges in the discrete transmitter characterization signal and by choosing the phase of the regenerated clock signal to be equal thereto.

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Eindhoven, Netherlands

Gerardus C Gielis