Cab-tek, Inc.

Arris, Inc.

Gerardo Vizcaino

Theodore J Goodlander

Jose M Valdepenas

Ricardo E McCaskey

This disclosure relates to a method and apparatus for improving the security of credit card transactions. It involves a so-called 'smart' credit card, which includes a processor, a memory, and a display window. When used, the card produces a verification number, which is based on a transaction sequence number and an encryption algorithm stored in the memory of the card. The verification number produced by the card is read in the display window and transmitted to a verification computer. The computer uses the verification number, together with a de-encryption algorithm, to produce a computed transaction sequence number. If the computed transaction sequence number corresponds to a transaction sequence number stored in the memory of the computer, then the computer will authorize the transaction, otherwise it will not. Both the card and computer change their respective transaction sequence numbers, such as by incrementation, so that different transaction sequence numbers are stored in the respective memories, for the production of a different verification number for the next transaction.

Method and apparatus for securing credit card transactions

A storage system for dynamic and trasparent error correction has a number of first individual storage devices for information and a second individual storage device for error code bits that are used to correct the information when one of the storage devices detects an error. Each error code bit is generated from the information at respective bit positions across the first storage devices. Storage device controllers are connected between a user CPU interface and respective storage devices for operating them concurrently. The interface includes an interface CPU for controlling the storage device controllers and translating the interface convention of user CPU requests into the interface convention of the storage devices. A buffer memory is connected to data surface associated with the respective storage devices. The interface CPU includes logic for immediately acknowledging a write to the associated storage device upon the data being placed in the buffer memory. The interface CPU also includes logic for checking data in the buffer memory and indicating it as having been read from an associated storage device without an actual read, whereby the buffer memory acts as a cache.

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Nashua, NH, United States of America

Gerardo Vizcaino