General Dynamics C4 Systems, Inc.

Altera Corporation

General Dynamics Government Systems Corporation

Gerardo Orlando

David Richardson King

Mark Krumpoch

Sridhar Krishnamurthy

Venkat Yadavalli

Ken Clauss

Peter Markou

Evan Custodio

Christof Paar

A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.

Wide band deterministic interface

A processing system () includes an input interface (), a first processor (), a second processor (), and an output interface () arranged in a serial configuration. Each of the input interface (), first processor (), second processor (), and output interface () computes a digest (, and) using information, e.g., a unique parameter (), known only by that element () and using information generated by that element (). The digests (and) are used to validate the integrity of payload data () processed by the system () to form processed data () and the system () only outputs the processed data () upon validation of data integrity. The serial configuration of system () may be implemented to provide high bit rate, redundant cryptographic services.

Serial architecture for high assurance processing

Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.

Systems and methods for efficiently creating digests of digital data

A method for reliable computation of point additions and point multiplications in an elliptic curve cryptography (ECC) system. Two asymmetric operations are performed: one of the operations is of slightly higher complexity than a conventional ECC operation, and the other operation is of much lower complexity than the first operation. The complexity of the second operation is a function of the desired degree of reliability, or the desired probability of failure detection. The method validates a computation involving one or more points on a specified elliptic curve by selecting a second elliptic curve, deriving a third elliptic curve from the specified and selected curves, projecting points onto the derived curve, performing a computation on the derived curve involving the projected points, validating the computation on the selected curve, extracting from the computation on the derived curve a predicted result of the computation on the selected curve, and comparing the predicted result to the computation on the selected curve. A predicted result of the computation to be validated may then be extracted from the computation on the derived curve. The predicted result is compared to an actual result of a computation on the selected curve, and if the results match, the predicted result of the computation performed on the selected curve is validated.

Reliable elliptic curve cryptography computation

A scalable multiplier architecture for the Galois field GF(2 ) is implemented in a programmable circuit. This architecture may be used in an implementation of public-key cryptosystems which use programmable multipliers in large Galois fields. This architecture is also fine grain scalable in both the time and the area (or logic) dimensions.

Growing community of inventors

Newton, MA, United States of America

Gerardo Orlando