Applied Materials, Inc.

Lam Research Corporation

Gerardo Delgadino

Yan Ye

Eric A Hudson

Xiaoye Zhao

Andrew D Bailey, Iii

Rajinder Dhindsa

Daniel John Hoffman

Alexei Marakhtanov

Douglas A Buchberger, Jr

Li-Qun Xia

Ashok K Sinha

Matthew L Miller

Lumin Li

Sang Ki Nam

Ryan Bise

Mike Kellogg

Daniel Le

Jim Rogers

Ellie Y Yieh

Shiang-Bau Wang

Yunsang Kim

Steven C Shannon

Anthony De La Llera

Tzu-Fang Huang

Alan John Jensen

Kang-Lie Chiang

Darrell Ehrlich

Jeremiah T P Pender

Robert C Hefty

Neungho Shin

Chunshi Cui

Wen H Zhu

Indrajit Lahiri

Teh-Tien Su

Joey Chiu

Fang Tian

Ying Xiao

Hee Yeop Chae

Xin Zhang

Paul Raymond Besser

Bart Jan Van Schravendijk

James D Carducci

Reza Arghavani

Samantha SiamHwa Tan

Shawming Ma

Michael C Kutney

Jens Schneider

Ezra Robert Gold

Kenji Takeshita

Shashank C Deshmukh

Tom A Kamp

Douglas H Burns

Bing Ji

Yoshie Kimura

Stephen M Sirard

Dengliang Yang

Yifeng Zhou

Bi-Ming Yen

Jang Gyoo Yang

Mahmoud Dahimene

Siyi Li

Lihua Li

Hoiman Raymond Hung

Robert B Hagen

Bi Ming Yen

Yu Cheng

Maryam Moravej

Richard Gustav Hagborg

Karsten Schneider

Leonid Romm

Zhilin Huang

Giuseppina Conti

Lihua Li Huang

Brian Sy-Yuan Sheih

Harald Orkorn-Schmidt

Chang-Lin (Peter) Hsieh

Melissa Hagen

Stephen Thai

David McParland

John M Nagarah

Anthony Dela Llera

Jungmin Ko

Sy-Yuan Brian Shieh

A plasma processing system includes a plasma chamber having a substrate support, and a multi-zone gas injection upper electrode disposed opposite the substrate support. An inner plasma region is defined between the upper electrode and the substrate support. The multi-zone gas injection upper electrode has a plurality of concentric gas injection zones. A confinement structure, which surrounds the inner plasma region, has an upper horizontal wall that interfaces with the outer electrode of the upper electrode. The confinement structure has a lower horizontal wall that interfaces with the substrate support, and includes a perforated confinement ring and a vertical wall that extends from the upper horizontal wall to the lower horizontal wall. The lower surface of the upper horizontal wall, an inner surface of the vertical wall, and an upper surface of the lower horizontal wall define a boundary of an outer plasma region, which surrounds the inner plasma region.

Multi zone gas injection upper electrode system

A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.

A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.

Dielectric contact etch

A method for selectively etching SiN with respect to SiO or SiGe or Si of a structure is provided comprising providing a plurality of cycles of atomic layer etching. Each cycle comprises a fluorinated polymer deposition phase comprising flowing a fluorinated polymer deposition gas comprising a hydrofluorocarbon gas into the plasma processing chamber, forming the fluorinated polymer deposition gas into a plasma, which deposits a hydrofluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas into the plasma processing chamber and an activation phase comprising flowing an activation gas comprising at least one of NHor Hinto the plasma processing chamber, forming the activation gas into a plasma, wherein plasma components from NHor Hcause SiN to be selectively etched with respect to SiO or SiGe or Si, and stopping the flow of the activation gas into the plasma processing chamber.

Atomic layer etching of silicon nitride

A method for selectively etching SiO and SiN with respect to SiGe or Si of a structure is provided. A plurality of cycles of atomic layer etching is provided, where each cycle comprises a fluorinated polymer deposition phase and an activation phase. The fluorinated polymer deposition phase comprises flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas, forming the fluorinated polymer deposition gas into a plasma, which deposits a fluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas. The activation phase comprises flowing an activation gas comprising an inert bombardment gas and H, forming the activation gas into a plasma, wherein the inert bombardment gas activates fluorine in the fluorinated polymer which with the plasma components from Hcause SiO and SiN to be selectively etched with respect to SiGe and Si, and stopping the flow of the activation gas.

Hydrogen activated atomic layer etching

A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

Air gap spacer integration for improved fin device performance

The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Integrated etch/clean for dielectric etch applications

A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber.

Dual zone temperature control of upper electrodes

A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising COand CHis provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.

Method of stripping organic mask with reduced damage to low-K film

Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.

Triode reactor design with multiple radiofrequency powers

A method for controlling critical dimension (CD) of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack is provided. The intermediate mask layer is opened by selectively etching the intermediate mask layer with respect to the patterned photoresist mask. The functionalized organic mask layer is opened. The functionalized organic mask layer opening comprises flowing an open gas comprising COS, forming a plasma, and stopping the flowing of the open gas. The etch layer is etched.

Bi-layer, tri-layer mask CD control

A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.

Method for low-K dielectric etch with reduced damage

A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.

Removal of process residues on the backside of a substrate

In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

Methods to avoid unstable plasma states during a process transition

Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing Hgas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.

Methods for etching a dielectric barrier layer with high selectivity

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Santa Clara, CA, United States of America

Gerardo Delgadino