Koninklijke Philips Corporation N.V.

Silicon Hive B.v.

Gerard Veldman

Patrick Peter Elizabeth Meuwissen

Harm Johannes Antonius Maria Peters

Ramanathan Sethuraman

Aleksandar Beric

Carlos Antonio Alba Pinto

Srinivasan Balakrishnan

Ramanathan Setheraman

The present invention relates to a data processing device () comprising a processing unit () and a memory unit (), and to a method for controlling operation of a memory unit () of a data processing device. The memory unit () comprises a main memory (), a low- level cache memory (), which is directly connected to the processing unit () and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (), a high-level cache memory (), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.

Enhancing performance of a memory unit of a data processing device by separating reading and fetching functionalities

An array of data values, such as an image of pixel values, is stored in a main memory (). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region () of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations () is performed. Locations that store pixel data for locations in the image outside the region () are selected for replacement, selectively exempting from replacement cache locations () that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region. In a further embodiment the cache for locations inside the region contains sets of banks, each set for a respective line from the image, data from the lines being distributed in a cyclically repeating fashion over the banks.

Data processing apparatus that provides parallel access to multi-dimensional array of data values

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Eindhoven, Netherlands

Gerard Veldman